Digital Electronics and Computer Interfacing Tim Mewes 3. Digital Electronics.

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Digital Electronics and Computer Interfacing Tim Mewes 3. Digital Electronics

Digital Electronics and Computer Interfacing D flip-flop Q D Timing diagram E 0 1 D Q Q E D Q follows D when the flip-flop is enabled

Digital Electronics and Computer Interfacing Edge triggered SR flip-flop Two gated SR flip-flops with the second enable line inverted with respect to the first Q Q S R E

Digital Electronics and Computer Interfacing Edge triggered SR flip-flop Q S E R time Timing diagram Falling edge of the enable line triggers change of flip-flop!

Digital Electronics and Computer Interfacing JK flip-flop The outputs and are feed back to the input gates Q Q J K E Edge triggered flip-flop with no invalid state!

Digital Electronics and Computer Interfacing JK flip-flop Timing diagram Q J E K time

Digital Electronics and Computer Interfacing7 Q Q J K Q Q S R Flip-flop symbols SR flip-flop Circle & triangle indicates high-to-low edge triggered version Enable/clock input Triangle indicates low-to-high edge triggered version JK flip-flop Q Q D D flip-flop Round input indicates that the clock-level causes the transition

Digital Electronics and Computer Interfacing Flip-flop applications Switch debouncing: +5 V S R Q Q 1k 

Digital Electronics and Computer Interfacing Flip-flop applications Switch debouncing: +5 V S R Q Q Q S 0 5 V 0 0 Timing diagram R

Digital Electronics and Computer Interfacing Flip-flop applications Asynchronous counter (ripple counter) Q Q J K 1 Q Q J K 1 Q Q J K 1 Q Q J K 1 LSBMSBABCD E - clock A B C D =

Digital Electronics and Computer Interfacing Flip-flop applications Frequency divider Q Q J K 1 Q Q J K 1 Q Q J K 1 Q Q J K 1 LSBMSBABCD E – clock A B C D f/2 f/4 f/8 f/16 f