Sequential Design Motivation Sequential processing often more tractable than parallel Example Sequential processing sometimes only method that works Example.

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Presentation transcript:

Sequential Design Motivation Sequential processing often more tractable than parallel Example Sequential processing sometimes only method that works Example (generalization of parity)

Sequential Design Finite State Machines Elements states transitions output(s) Example

Sequential Design Finite State Machines Sequence recognition 1) Create machine to recognize sequence 2) Fill in other states Example (“abac”) Note: Must handle cases whereby non-initial substring is target sequence

Sequential Design Mealy and Moore Machines Moore output function of current state only Mealy output function of current state and current inputs

Sequential Design i) Derive the transition equations from the next state logic iii) Construct a transition/output table from the equations produced in i) and ii) ii) Derive the output equation from the output logic iv) Construct a state/output table by labeling the states in iii) v) Derive a DFSM from the table in iv) vi) State in ordinary language what the machine is doing

Sequential Design Sequential Machine Analysis Example

Sequential Design Sequential Machine Analysis Example i) Derivation of transition equations Q0 + = Q0I0'I1' + Q0Q1'I0' + Q0Q1'I1' + Q0'Q1I1 + Q0'Q1I0 + Q0'I0I1 Q1 + = Q1I0'I1' + Q1'I0'I1 + Q1I0I1 + Q1'I0I1'

Sequential Design Sequential Machine Analysis Example ii) Derivation of output equation OUT = Q0'Q1'

Sequential Design Sequential Machine Analysis Example iii) Construction of the transition/output table Q0 + = Q0I0'I1' + Q0Q1'I0' + Q0Q1'I1' + Q0'Q1I1 + Q0'Q1I0 + Q0'I0I1 Q1 + = Q1I0'I1' + Q1'I0'I1 + Q1I0I1 + Q1'I0I1' I0I1I0I1 Q0Q1Q0Q OUT Q0+Q1+Q0+Q1+

Sequential Design Sequential Machine Analysis Example iv) Construction of the state/output table A = 00 B = 01 C = 10 D = 11 I0I1I0I1 Q0Q1Q0Q OUT AABBC1 BBCCD0 CCDDA0 DDAAB0 Q0+Q1+Q0+Q1+

Sequential Design Sequential Machine Analysis Example v) Derivation of the finite state machine I0I1I0I1 Q0Q1Q0Q OUT AABBC1 BBCCD0 CCDDA0 DDAAB0 Q0+Q1+Q0+Q1+

Sequential Design Sequential Machine Analysis Example vi) Ordinary language description?

Sequential Design Sequential Machine Synthesis i) Finite state diagram construction ii) State/output table construction iii) State-variable assignment iv) Substitution of state-assignments into the state/output table v) Construct an excitation table vii) Derive output equations from the transition/output table vi) Derive excitation equations from this table viii) Draw a circuit diagram that realizes the excitation and output ix) Verification

Sequential Design Sequential Machine Synthesis Example 1 (parity) i) State diagram construction

Sequential Design Sequential Machine Synthesis Example 1 (parity) ii) Construction of the state/output table I Q0Q0 01OUT even odd0 even1 Q0+Q0+

Sequential Design Sequential Machine Synthesis Example 1 (parity) iii) State variable assignment 0 = even 1 = odd I Q0Q0 01OUT even odd0 even1 Q0+Q0+

Sequential Design Sequential Machine Synthesis Example 1 (parity) iv) Transition/output table construction I Q0Q0 01OUT Q0+Q0+

Sequential Design Sequential Machine Synthesis Example 1 (parity) v) Excitation/output table construction I Q0Q0 01OUT D0D0

Sequential Design Sequential Machine Synthesis Example 1 (parity) vi) Excitation equation derivation I Q0Q0 01OUT D0D0 D0 = Q0I' + Q0'I

Sequential Design Sequential Machine Synthesis Example 1 (parity) vii) Output equation derivation I Q0Q0 01OUT D0D0 OUT = Q0

Sequential Design Sequential Machine Synthesis Example 1 (parity) viii) Circuit realization OUT = Q0 D0 = Q0I' + Q0'I

Sequential Design Sequential Machine Synthesis Example 1 (parity) ix) Verification I Q OUT

Sequential Design Sequential Machine Synthesis Example 2 (sequence recognition) i) Convert DFSM into binary

Sequential Design Sequential Machine Synthesis Example 2 (sequence recognition) ii) Construct excitation/output table I0I1I0I1 Q0Q1Q2Q0Q1Q OUT D0D1D2D0D1D2

Sequential Design Sequential Machine Synthesis Example 2 (sequence recognition) iii) Derive minimized excitation and output equations Note: x’s represent don’t care conditions

Sequential Design Sequential Machine Synthesis Example 2 (sequence recognition) iv) All equations and circuit D0 = I0Q1Q2 D1 = I1Q2 + I0'I1'Q1Q2' D2 = I0'I1' OUT = Q0

Sequential Design Sequential Machine Synthesis Example 2 (sequence recognition) v) Verification I0I I1I inputbababacabacc Q0Q Q1Q Q2Q stateINITaababaababaabacaababaabacINIT OUT

Sequential Design Sequential Machine Synthesis Example 3 (JK flip-flop design) Setting states QQ+Q+ JK 000x 011x 10x1 11x0 Q+ ≡ QN J + QK'

Sequential Design Sequential Machine Synthesis Example 3 (JK flip-flop design) Mod 4 example I0I1I0I1 Q0Q1Q0Q OUT Q0+Q1+Q0+Q1+

Sequential Design Sequential Machine Synthesis Example 3 (JK flip-flop design) Mod 4 example, excitation table I0I1I0I1 Q0Q1Q0Q x,0x0x,1x 1x,1x 010x,x01x,x0 1x,x1 11 x0,x0x0,x1 x1,x1 10x0,0xx1,0x x1,1x J0 K0, J1 K1

Sequential Design Sequential Machine Synthesis Example 3 (JK flip-flop design) Mod 4 example, excitation equations J0 = I0I1 + I1Q1 + I0Q1 K0 = I0I1 + I0Q1' + I1Q1' J1 = I0I1 + + I1Q0' + I0Q0' K1 = I0I1 + I1Q0 + I0Q0

Sequential Design Sequential Machine Synthesis Example 3 (JK flip-flop design) Mod 4 example, realization

Sequential Design Summary of Topics Finite state machines Sequential machine analysis Sequential machine synthesis D flip-flops JK flip-flops