Lecture 20: Sequential Logic (5) CPE 201 Digital Design Lecture 20: Sequential Logic (5)

Lecture Outline Excitation Tables Controller Design Examples State Reduction

Understanding the Controller’s Behavior x=0 x=0 s0 s1 b x n1 n0 x=1 x=0 ’ 01 00 10 11 On2 On1 O ff On3 1 clk st a t e=01 s0 s1 b x n1 n0 x=1 ’ 01 10 11 On2 On1 O ff On3 clk b ’ 00 00 O ff b b 1 x=1 x=1 x=1 01 On1 10 On2 11 On3 b x n1 1 n0 s1 s0 clk 1 clk st a t e=00 st a t e=00 I nputs: b O utputs: x

Controller Example: Button Press Synchronizer bi bo Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button actually pressed We assumed such an ideal button press signal in earlier example, like the button in the laser timer controller

Controller Example: Button Press Synchronizer (cont.) Step 2: Create architecture Combinational logic n0 s1 s0 n1 bo bi clk State register FSM inputs outputs Step 1: FSM A B C bo=1 bo=0 bi b i ’ FSM inputs: bi; FSM outputs: bo Step 5: Create combinational circuit clk State register bo bi s1 s0 n1 n0 Combinational logic n1 = s1’s0bi + s1s0’bi n0 = s1’s0’bi bo = s1’s0bi’ + s1’s0bi = s1’s0 Step 4: State table Step 3: Encode states 00 01 10 bo=1 bo=0 bi ’ FSM inputs: bi; FSM outputs: bo

Sequence Decoder Example Design a circuit to detect three or more consecutive 1’s in a string of bits coming through an input line Present State Input Next State Output A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 1 A(t+1)= Σ(3,5,7) B(t+1)= Σ(1,5,7) Y(A,B,x)= Σ(6,7)

Synthesis Using D Flip-Flops Need 2 D flip-flops to represent the four states A(t+1)=DA(A,B,x)= Σ(3,5,7) B(t+1)=DB(A,B,x)= Σ(1,5,7) Y(A,B,x)= Σ(6,7) DA = Ax + Bx DB = Ax + B’x y = AB

Sequence Detector Logic Diagram DA = Ax + Bx DB= Ax + B’x y=AB

Excitation Tables Using flip-flops other than D can be complicated Why? Input equations for the circuit must be derived indirectly from the state table Excitation tables can help They give us the flip-flop input that would cause a state transition Combinational logic State register s1 s0 n1 n0 x b clk FSM inputs outputs DA DB JA JB KA KB

Excitation Tables – JK Flip-Flop During design we know the transition Q(t)  Q(t+1) and want to know inputs JK that lead to the transition Q(t+1) = JQ’(t) + K’Q(t) Excitation table Q(t) Q(t+1) J K Input situation 1 X Reset, No change 1 X Set, Complement X 1 Reset, Complement X Set, No change

Excitation Tables – T Flip-Flop Q(t+1) = TQ’(t) + T’Q(t) = T XOR Q Excitation table Q(t) Q(t+1) T Input situation 1 No change 1 Complement 1 Complement No change

Synthesis Using JK Flip-Flops Present State Input Next State Flip-Flop Inputs A B x A B JA KA JB KB 0 0 0 0 0 0 x 0 x 0 0 1 0 1 0 x 1 x 0 1 0 1 0 1 x x 1 0 1 1 0 1 0 x x 0 1 0 0 1 0 x 0 0 x 1 0 1 1 1 x 0 1 x 1 1 0 1 1 x 0 x 0 1 1 1 0 0 x 1 x 1 We have to include J, K input conditions, derived from the excitation table Available from the FSM diagram

Synthesis Using JK Flip-Flops

Synthesis Using JK Flip-Flops

Synthesis Using T Flip-Flops E.g.: 3-bit Binary Counter The counter counts with the clock State diagram

Synthesis Using T Flip-Flops Present State Next State Flip-Flop Inputs A2 A1 A0 A2 A1 A0 TA2 TA1 TA0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 State diagram

Synthesis Using T Flip-Flops

Controller Example: Sequence Generator Want to generate sequence 0001, 0011, 1100, 1000, (repeat) Each value for one clock cycle Step 2: Create architecture Combinational logic n0 s1 s0 n1 clk State register w x y z Step 1: Create FSM A B D wxyz=0001 wxyz=1000 wxyz=0011 wxyz=1100 C Inputs: none; Outputs: w,x,y,z A B D wxyz=0001 wxyz=1000 wxyz=0011 wxyz=1100 C Inputs: none; Outputs: w,x,y,z Step 3: Encode states 00 01 10 11 clk State register w x y z n0 s0 s1 n1 w = s1 x = s1s0’ y = s1’s0 z = s1’ n1 = s1 xor s0 n0 = s0’ Step 4: Create state table Step 5: Create combinational circuit

Controller Example: Secure Car Key (from earlier example) K1 K2 K3 K4 r=1 r=0 Wait Inputs: a; Outputs: r a ’ Step 1 Step 4 Combinational logic s2 s1 s0 n2 r a n1 n0 clk State register Step 2 a ’ r=0 r=1 000 001 010 011 100 I nputs: ; O utputs: r Step 3 We’ll omit Step 5

FSM Example: Code Detector Unlock door (u=1) only when buttons pressed in sequence: start, then red, blue, green, red Input from each button: s, r, g, b Also, input a indicates that some colored button pressed FSM Wait for start (s=1) in “Wait” Once started (“Start”) If see red, go to “Red1” Then, if see blue, go to “Blue” Then, if see green, go to “Green” Then, if see red, go to “Red2” In that state, open the door (u=1) Wrong button at any step, return to “Wait”, without opening door s Start u r Door Red Code g lock Green detector b Blue a Wait Start Red1 R ed2 Green Blue s ’ a r b g ab ag ar u=0 u=1 Inputs: s,r,g,b,a; Outputs: u Q: Can you trick this FSM to open the door, without knowing the code? A: Yes, hold all buttons simultaneously

Improve FSM for Code Detector Inputs: s,r,g,b,a; Outputs: u Wait s’ ar’ ab’ ag’ ar’ u=0 s Start a ’ u=0 ar ab ag ar Red1 Blue Green Red2 a ’ a ’ a ’ u=0 u=0 u=0 u=1 New transition conditions detect if wrong button pressed, returns to “Wait”

Common Pitfalls Regarding Transition Properties At most one condition must be true For all transitions leaving a state At least one condition must be true b If ab=11 next state=? a ’ b a What if ab=00? ’ b a ’b ’ b

Verifying Correct Transition Properties Can verify using Boolean algebra At most one condition true AND of each condition pair (for transitions leaving a state) should equal 0  proves pair can never simultaneously be true At least one condition true OR of all conditions of transitions leaving a state should equal 1  proves at least one condition must be true Example a * a’b = (a * a’) * b = 0 * b = 0 OK! Answer: a + a’b = a*(1+b) + a’b = a + ab + a’b = a + (a+a’)b = a + b Fails! Might not be 1 (i.e., a=0, b=0) Q: For shown transitions, prove whether: * At most one condition true (AND of each pair is always 0) * At least one condition true (OR of all transitions is always 1)

Evidence that Pitfall is Common Recall code detector FSM We “fixed” a problem with the transition conditions Do the transitions obey the two required transition properties? Consider transitions of state Start, and the “at most one true” property Wait s ’ u=0 s Start a ’ u=0 ar ab ag ar Red1 Blue Green Red2 a ’ a ’ a ’ u=0 u=0 u=0 u=1 ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g) = (a*a’)r = 0*(r’+b+g) = (a*a)*r*(r’+b+g) = a*r*(r’+b+g) = 0 = 0 = arr’+arb+arg = 0 + arb+arg = arb + arg = ar(b+g) Fails! Means that two of Start’s transitions could be true Intuitively: press red and blue buttons at same time: conditions ar, and a(r’+b+g) will both be true. Which one should be taken? Q: How to solve? a A: ar should be arb’g’ (likewise for ab, ag, ar)

Simplifying Notations FSMs Assume that unassigned output is implicitly 0 Sequential circuits Assume that unconnected clock inputs are implicitly connected to same external clock

State Reduction and Assignment Goal: Reduce the number of states while keeping the external input-output requirements 2m states need m flip-flops, so reducing the states may reduce flip-flops If two states are equivalent, one can be removed What are equivalent states?

State Reduction Example For state reduction only input-output sequences are important States are only used to provide the output sequence 010101110100 applied and start from state a State a a b c d e f f g f g a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0

State Reduction Example Present State Next State Output x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1 States e and g are equal since for each member of the set of inputs, they give the same output and send the circuit either to the same state or an equivalent state

State Reduction Example Present State Next State Output x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f e f 0 1 Table and state diagram after the first reduction: g is removed and replaced by state e. NEW equal states: d and f

State Reduction Example Present State Next State Output x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1 If we apply the same input sequence: State a a b c d e d d e d e a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0 Reduced state diagram Table and state diagram after the second reduction: f is removed and replaced by state d.

Design Procedure From word description, derive state diagram Reduce the number of states Assign binary values to states Obtain the binary coded state table Choose the type of flip-flop used Derive the simplified flip-flop input and output equations Draw the logic diagram

Chapter Summary Sequential circuits Have state Created robust bit-storage device: D flip-flop Put several together to build register, which we used to hold state Defined FSM formal model to describe sequential behavior Using mathematical models – Boolean equations for combinational circuit, and FSMs for sequential circuits Defined step process to convert FSM to sequential circuit Controller So now we know how to build sequential circuits (known as controllers)

Readings Chapter 5 Sections 5.8