C HAPTER F IVE S YNCHRONOUS S EQUENTIAL L OGIC 1

F LIP -F LOP C HARACTERISTIC T ABLES DQ Q DQ(t+1) Reset Set JKQ(t+1) 00Q(t)Q(t) Q’(t) No change Reset Set Toggle JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) No change Toggle 2

F LIP -F LOPS WITH D IRECT I NPUTS Asynchronous Reset DQ Q R Reset RDCLKQ(t+1) 0xx0 3

F LIP -F LOPS WITH D IRECT I NPUTS Asynchronous Reset DQ Q R Reset RDCLKQ(t+1) 0xx0 10 ↑ 0 11 ↑ 1 4

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS A logic diagram is recognized as a clocked sequential circuit if it includes flip-flops. The flip- flops may be of any type, and the logic diagram may or may not include combinational logic gates. The behavior of a clocked sequential circuit is determined from the inputs, the outputs, and the state of its flip-flops. The outputs and the next state are both a function of the inputs and the present state. The analysis of a sequential circuit consists of obtaining a state table and a state diagram for the time sequence of inputs, outputs, and internal states. 5

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS The State State = Values of all Flip-Flops Example A B = 0 0 6

The behavior of a clocked sequential circuit can be described algebraically by means of state equations. A state equation (also called a transition equation) specifies the next state as a function of the present state and inputs. 7

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS Flip-Flop input equations D A = A(t) x(t)+B(t) x(t) = A x + B x D B = A’(t) x(t) = A’ x State equations A(t+1) = D A B(t+1) = D B Output equation y(t) = [A(t)+ B(t)] x’(t) = (A + B) x’ 8

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Input Next State Output ABxABy t+1 t t

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy t+1 t t 10

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS State Diagram /00/0 0/10/1 1/01/0 1/01/0 1/01/0 1/01/00/10/1 0/10/1 AB input/output Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS D Flip-Flops Example : DQ Q x CLK y A Present State Input Next State AxyA ,11 01,10 A(t+1) = D A = A  x  y 12

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS JK Flip-Flops Example : J A = BK A = B x’ J B = x’K B = A  x A(t+1) = J A A’ + K’ A A = A’B + AB’ + Ax B(t+1) = J B B’ + K’ B B = B’x’ + ABx + A’Bx’ Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS JK Flip-Flops Example : Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS T Flip-Flops Example : T A = B xT B = x y = A B A(t+1) = T A A’ + T’ A A = AB’ + Ax’ + A’Bx B(t+1) = T B B’ + T’ B B = x  B Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y

A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS T Flip-Flops Example : Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y /00/0 1/01/0 0/00/0 1/01/0 1/01/0 1/11/1 0/00/0 0/10/1 16

T HE P ROBLEMS : 5.3, 5.4, , 5.9, 5.10,

P RIORITY E NCODERS 4-Input Priority Encoder ( V is a valid bit indicator) PriorityEncoder VyxVyx D3D2 D1D0D3D2 D1D0 V: is the valid bit indicator that is set to 1 when one or more inputs are equal to 1. 18

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C HAPTER S IX R EGISTERS AND C OUNTERS 21

A clocked sequential circuit consists of a group of flip-flops and combinational gates connected to form a feedback path. A circuit with flip-flops is considered a sequential circuit even in the absence of combinational gates. Circuits that include flip-flops are classified by the function they perform. Two such circuits are registers and counters. 22

A register is a group of flip-flops, each one of which is capable of storing one bit of information. An n-bit register consists of a group of n flip-flops. A register consists of a group of flip-flops together with gates that affect their operation. (they determine how the information is transferred into register). A counter is a special type of register that goes through a predetermined sequence of binary states. 23

24 Four-bit register

R EGISTER WITH PARALLEL LOAD The transfer of new information into a register is referred to as loading or updating the register. If all the bits of the register are loaded simultaneously with a common clock pulse, we say that the loading is done in parallel. 25 CLEAR or RESET. When CLEAR is 0 the flip flop is resetting independent of clock and D values. It is useful because in digital systems when the power is turned on the state of flip-flops is unknown. Direct input CLEAR can bring all flip-flops to the known starting state prior to the clock operation.

26 Four-bit register with parallel load Two channel mux