Programmable Interrupt Controller (PIC) - 8259

Programmable Interrupt Controller (PIC) 8259 is Programmable Interrupt Controller (PIC) It is a tool for managing the interrupt requests. 8259 is a very flexible peripheral controller chip: PIC can deal with up to 64 interrupt inputs interrupts can be masked various priority schemes can also programmed. originally (in PC XT) it is available as a separate IC Later the functionality of (two PICs) is in the motherboards chipset. In some of the modern processors, the functionality of the PIC is built in.

FIGURE : Block diagram and pin definitions for the 8259A Programmable Interrupt Controller (PIC). (Courtesy of Intel Corporation.)

Architecture of PIC-8259 Features: It is programmed to work with either 8085 or 8086 processor. It manage 8-interrupts according to the instructions written into its control registers. In 8086 processor, it supplies the type number of the interrupt and the type number is  programmable. The interrupts can be masked or unmasked individually. The 8259s can be cascaded to accept a maximum of 64 interrupts. FUNCTIONAL BLOCK DIAGRAM OF 8259: It has eight functional blocks. They are: Control logic Read Write logic Data bus buffer Interrupt Request Register (IRR) In-Service Register (ISR) Interrupt Mask Register (IMR) Priority Resolver (PR) Cascade buffer.

Architecture of PIC-8259 Data Bus Buffer: Read/Write control logic: Data bus and its buffer are used for the following activities: It is a tristate bidirectional buffer interfaces internal 8259A to the microprocessor system data bus The processor sends control word to data bus buffer through D0-D7. The processor read status word from data bus buffer through D0-D7 From the data bus buffer the 8259 send type number through D0-D7 to the processor. Read/Write control logic: The function of this block is to accept OUTput commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 8259A to be transferred onto the Data Bus.

Architecture of PIC-8259 Interrupt request register: The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go high, the request is stored in IRR in order to serve them one by one on the priority basis. It registers a request only if the interrupt is unmasked. Normally IR0 has highest priority and IR7 has the lowest priority. The priorities of the interrupt request input are also programmable. First the 8259 should be programmed by sending Initialization Command Word (ICW) and Operational Command Word (OCW). These command words will inform 8259 about the following:           Type of interrupt signal (Level triggered / Edge triggered). Type of processor (8085/8086). Call address and its interval (4 or 8) Masking of interrupts. Priority of interrupts. Type of end of interrupts.

Architecture of PIC-8259 Interrupt mask register (IMR): The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be masked. The relevant information is send by the processor through OCW. In-service register(ISR): The in-service register keeps track of which interrupt is currently being serviced. Priority resolver: The priority resolver examines the interrupt request, mask and in-service registers and determines whether INT signal should be sent to the processor or not. The IR0 has the highest priority while the IR7 has the lowest priority, normally in fixed priority mode. The priorities however may be altered by the programming the 8259A in rotating mode.

Architecture of PIC-8259 Cascade buffer/comparator: The cascade buffer/comparator is used to expand the interrupts of 8259. In cascade connection one 8259 will be directly interrupting 8086 and it is called master 8259. To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be connected. The 8259s interrupting the master 8259 are called slave 8259s. Each 8259 has its own addresses so that each 8259 can be programmed independently by sending command words and independently the status bytes can be read from it.

Pin description CS (CHIP SELECT) : A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device is selected. WR (WRITE): A LOW on this input enables the CPU to write control words (ICWs and OCWs) to the 8259A. RD (READ) : A LOW on this input enables the 8259A to send the status of the Interrupt Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus. A0: This input signal is used in conjunction with WR and RD signals to write commands into the various command registers, as well as reading the various status registers of the chip. This line can be tied directly to one of the address lines.

Pin description D7 - D0: BIDIRECTIONAL DATA BUS- Control, status and interrupt-vector information is transferred via this bus. CAS0 - CAS2: CASCADE LINES: The CAS lines form a private 8259A bus to control a multiple 8259A structure. These pins are outputs for a master 8259A and inputs for a slave 8259A. SP/EN: SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it can be used as an output to control buffer transceivers (EN). When not in the buffered mode it is used as an input to designate a master (SP e 1) or slave (SP e 0). INT: INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU, thus it is connected to the CPU's interrupt pin. INTA: INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A interrupt-vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the CPU.

INTERRUPT SEQUENCE The events occur as follows in an 8086 system: 1. One or more of the INTERRUPT REQUEST lines (IR7 – IR0) are raised high, setting the corresponding IRR bit(s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the corresponding IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus through its D7 - D0 pins. 5. This CALL instruction will initiate second INTA pulses to be sent to the 8259A from the CPU group. 6. This INTA pulse allow the 8259A to release an 8-bit preprogrammed subroutine address onto the Data Bus. 7. ISR bit is reset at the end of the 2nd INTA pulse if automatic EOI mode is programmed

8255- Programmable Peripheral Interface

Hand shaking Many I/O devices accept or release information slower than the microprocessor. A method of I/O control called handshaking or polling, synchronizes the I/O device with the microprocessor. An example is a parallel printer that prints a few hundred characters per second (CPS). The processor can send data much faster. a way to slow the microprocessor down to match speeds with the printer must be developed

Hand shaking I/O synchronization is achieved by implementing what is known as handshaking as part of the input/output interface. E.g. - Parallel printer interface

8255- Programmable Peripheral Interface The 8255 is a widely used, programmable parallel I/O device. It can be programmed to transfer data under data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile and economical (when multiple I/O ports are required). It is an important general purpose I/O device that can be used with almost any microprocessor.

8255- Programmable Peripheral Interface

8255- Programmable Peripheral Interface This 8255 has 24 input/output lines, which can be individually programmed. These I/O lines can be grouped as Group A and Group B. Group A contains an 8-bit port A along with a 4-bit port C upper. Group B contains an 8-bit port B along with a 4-bit port, c lower. The C upper and C lower ports can be combined be use as an 8-bit port. Thus for on 8255 we can have either three 8 bit I/O ports or two 8 bit and two 4 bit ports. All these ports can function independently either as input or as output ports. This can be achieved by programming the bits of an internal register called as Control Word Register (CWR).

Signal Description of 8255 The Read/write control logic is having six signal lines. Which are RD, WR, RESET, CS, A0 and A1 RD [READ] :- This control signal enables the read operation. When the signal is low, the microprocessor reads data from a selected I/O port of 8255 WR [WRITE] :- This control signal enables the write operation. When the signal goes low the MPU (microprocessor) writes into a selected I/O port or the control register. RESET :- This is an active high signal, A logic high on this line clears the control word register and set all ports in the input mode. (that is , set as input port by default after reset)   CS [CHIP SELECT] :- This is a Chip Select line. If the line goes low it enables the 8255 to respond to RD and WR signals. A1 – A0 :- These are address lines driven by the microprocessor. These address lines are used for selecting any one of the three ports or a control word.

Signal Description of 8255 PA7 – PA0 :- These are eight port A lines that act either as input or output lines depending up on the control word loaded into the control word register. PC7 – PC4 :- These are four Port C upper lines that can act as input or output lines. This port can be used for the generation of handshake lines.   PC3 – PCo : - These are four port C lower lines that can act as input or output lines. This port can also be used for the generation of handshake lines. PB0 – PB7 :- These are 8 port B lines which can be input or output lines in the same way as port A D0 – D7 :- These are the data bus lines that carry data or control word to/from the microprocessor. This 8255 is a widely used, flexible and economical I/O device that can be used with almost all microprocessors when multiple I/O ports are required. 8255 is a 40 pin IC.

MODES OF OPERATION OF 8255 All the functions of 8255 A is classified according to two modes: the Bit Set/Reset (BSR) mode and the I/O mode. The BSR mode is used to set or reset the bits in port C. The I/O mode is further divided into three modes: Mode 0, Mode 1 and Mode 2. In Mode 0, all ports function as simple as I/O ports. Mode 1 is a handshake mode whereby port A and port B use bits from port C as handshake signals. In the handshake mode, two types of I/O data transfer can be implemented: status checks and interrupt. In Mode 2 port A can be set up for bidirectional data transfer using handshaking signals from port C and port B can be set up either in Mode 0 or Mode 1.

Mode 0 : Simple Input or Output This is also called basic I/O mode. In this mode, ports A and B are used as two simple 8-bit I/O ports and port C as two 4-bit ports. Each port (or half-port in case of C) can be programmed to function as simply an input or an output port. The input/output features in Mode 0 as follows: Output is latched. Inputs are not latched. Ports do not have handshake or interrupt capability. Any port can be used as input or output port. 4-bit can combined used as a third 8-bit port.

Mode 1: Input or Output with handshake This is also called strobe I/O mode. In Mode 1: handshake signals are exchanged between the MPU and peripherals prior to data transfer. The features of this mode include the following: Two ports (A and B) function as 8-bit I/O ports. They can be configured either as input or output ports. Each port uses three lines from port C as handshake signals. The remaining two lines of port C can be used for simple I/O functions. Input and output data are latched. Interrupt logic is supported. In the 8255, the specific lines from port C used for handshake signals vary according to the I/O function of a port.

Mode 2: Bidirectional Data Transfer This is also called strobe bi-directional I/O mode. This mode is used primarily in applications such as data transfer between two computers of floppy disk controller interface. In this mode, Port A can be configured as the bidirectional port and port B either in Mode 0 or Mode 1. Port A uses five signals from port C as handshake signals for data transfer. The remaining three signals from port C can be used as simple I/O or as handshake for port B.