Chapter 7. Differential and multistage amplifiers

Contents The MOS differential pair Small-signal operation of the MOS differential pair The BJT differential pair Other non-ideal characteristics of the differential amplifier The differential amplifier with active load Multistage amplifiers

Introduction Differential pair는 아날로그 IC에서 가장 흔하게 쓰이는 블록임. 초고속 switching 소자인 ECL(emitter-coupled logic)의 기초가 됨. 1940년대 진공관 형태로 발명되었으나 추후 discrete BJT로 구현됨. 특히 집적 회로가 발명된 이후 매우 널리 쓰임. Differential pair의 성능은 두 트랜지스터의 특성이 얼마나 일치하 느냐에 달려있음. 여러 부품을 필요로 함. Differential 증폭기의 장점 Single-ended 회로에 비해 잡음과 간섭에 강함. Multi-stage 구성 시 by-pass capacitor나 coupling capacitor 필요 없음.

uA741 chip layout

MOS differential pair Current mirror (active load)로 구현 Q1, Q2가 matched transistor라고 가정 Saturation 영역에서 동작시킴 Current mirror로 구현

Operation with a common-mode input voltage Q1, Q2가 saturation 영역인 경우 VCM을 바꿔도 출력 전압은 전류에만 의존하므로 변동 없음. 최고 입력 전압 : 최저 입력 전압 : (Current source I의 최소 출력 전압에 의해 결정됨.)

Operation with a differential input voltage 최고 입력 전압 : (Q1전류는 I, Q2전류는 0일 때 전압임.) 최저 입력 전압 : Q1전류 0, Q2전류가 I인 경우임.

Large signal operation

1차 함수 근사식

2. Small signal operation = =

Common mode Differential mode

Differential mode equivalent Differential mode half circuit

Example 7.2 Q1, Q2가 matched transistor이다. ro가 매우 클 때 differential mode 전압 이득을 구하라.

2.3 differential amplifier with current-source loads

2.4 cascode differential amplifier

2.5 Common-mode gain and CMRR CMRR : Common mode rejection ratio

Common mode half circuit

Effect of mismatch (CMRR) RD mismatch CMRR : Common mode rejection ratio

gm mismatch

3. BJT differential pair Q1, Q2가 matched transistor linear active영역에서 동작시킴

Basic operation Different modes of operation of the BJT differential pair: (a) the differential pair with a common-mode input voltage VCM; (b) the differential pair with a “large” differential input signal;

Input common mode range (c) the differential pair with a large differential input signal of polarity opposite to that in (b); (d) the differential pair with a small differential input signal vi. Note that we have assumed the bias current source I to be ideal (i.e., it has an infinite output resistance) and thus I remains constant with the change in VCM. Input common mode range Q1이 saturation되는 전압. Current source I가saturation되는 전압.

3.3 Large signal operation

Extension of linear range The transfer characteristics of the BJT differential pair can be linearized (i.e., the linear range of operation can be extended) by including resistances in the emitters.

3.4 Small signal operation

Small signal equivalent A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal vid; dc quantities are not shown.

Small signal equivalent of DP with emitter resistor

Differential half circuit

Single-ended로 접속해도 REE>>re 이면 앞 페이지와 동일

Common-mode gain and CMRR

(a) Definition of the input common-mode resistance Ricm (a) Definition of the input common-mode resistance Ricm. (b) The equivalent common-mode half-circuit.

Example 7.4 Assume β = 100. Evaluate the following: (a) The input differential resistance Rid . (b) The overall differential voltage gain vod/ vsig (neglect the effect of ro). (c) The worst-case common-mode gain if the two collector resistances are accurate to within ±1%. (d) The CMRR, in dB. (e) The input common-mode resistance (assuming that the Early voltage VA = 100 V).

4. Other Non-ideal Characteristics of the Differential Amplifier 4.1 Input Offset Voltage of the MOS Differential Pair Output offset voltage RD mismatch : (W/L) mismatch : Vt mismatch :

Input offset voltage RD mismatch : (W/L) mismatch : Vt mismatch : Application of a voltage equal to the input offset voltage VOS to the input terminals with opposite polarity reduces VO to zero.

4.2 Input offset voltage of the bipolar differential pair 4.3 Input bias and offset currents of the bipolar differential amplifier

5. The Differential Amplifier with Active Load 출력 전압을 differential mode로 얻을 때 장점 Common-mode gain이 줄어들어 CMRR이 증가한다. Differential mode gain 이 2배 (6 dB) 증가한다. (각 트랜지스터 출력 전압이 크기는 같고 반대 부호임.) Differential mode 신호 전송이 잡음이나, 간섭 신호에 영향을 덜 받으므로 op-amp같은 증폭기 IC에서 첫번째 단계로 differential amp가 흔하게 사용된다. 그러나 차동 모드를 지원하지 않고 single-ended 모드를 지원하는 다른 부품으로 연결하는 경우 적절한 변환 장치가 필요하다. Figure 7.30 A three-stage amplifier consisting of two differential-in, differential-out stages, A1 and A2, and a differential-in, single-ended-out stage A3.

Non-ideal property – cross-talk Far end crosstalk voltage Voltage Near end crosstalk voltage 인접한 전선들 사이에 간섭이 생긴다.

5.1 Differential to Single-Ended Conversion Figure 7.31 A simple but inefficient approach for differential to single-ended conversion.

5.2 The active-loaded MOS differential pair (a) The active-loaded MOS differential pair. (b) The circuit at equilibrium assuming perfect matching. (c) The circuit with a differential input signal applied and neglecting the ro of all transistors.

5.3 Differential gain of the active-loaded MOS pair Q4의 전류는 Q3의 υgs에 의해 정해짐. Trans-conductance Gm : Output equivalent circuit of the differential amplifier with active-loaded pair for differential input signals.

Output resistance Ro : Differential gain :

5.4 Common-Mode Gain and CMRR

5.5 The bipolar differential pair with active load

Differential gain : Common-Mode Gain and CMRR:

Systematic Input Offset Voltage Current mirror의 base current로 전류 오차 있음.

Output resistance를 증가시키기 위해 cascode 전류 오차에 의한 offset을 줄이기 위해 Wilson current-mirror Figure 7.40 An active-loaded bipolar differential amplifier employing a folded cascode stage (Q3 and Q4) and a Wilson current-mirror load (Q5, Q6, and Q7).

6 Multistage amplifiers 실제 트랜지스터 증폭기는 여러 단으로 구성됨 1단은 전압 이득 및 높은 입력 저항 제공으로 신호원의 내부 저항에 의한 전압 감쇄를 억제함. Differential amplifier인 경우 common mode rejection 기능도 제공해야 함. 중간 단계는 높은 전압 이득 제공 기능. 경우에 따라 differential mode 를 single-ended mode로 변환하는 기능을 제공하기도 함. DC 전압 레 벨을 바꾸어 ± 전압 스윙이 가능하도록 하는 기능 제공. 마지막 단계는 부하 저항이 작은 경우 전압 강하를 피하기 위해 낮은 출력 임피던스를 제공. 대전류 공급 기능 제공.

6.1 Example : a two-stage CMOS Op amp 1st stage 2nd stage

Input offset voltage 를 없애는 조건 Common mode입력 전압에 대해 출력 전압이 0이 되어야 함.

A Bias circuit that stabilizes gm DC bias circuit : 전원 전압 변화와 MOSFET의 Vt와 상관없이 바이어스 전류를 공급 트랜지스터의 gm들이 저항 1개와 트랜지스터 크기에 의해 정해짐

6.2 Example : a bipolar Op amp Differential amp Differential amp (differential in, single ended out) Amp, level shifting Voltage buffer Figure 7.43 A four-stage bipolar op amp.

Example 7.6 : a bipolar Op amp

Example 7.7 Use the dc bias quantities evaluated in Example 7.6 to analyze the circuit in Fig. 7.43, to determine the input resistance, the voltage gain, and the output resistance.