1 CSE370, Lecture 26 Lecture 26 u Logistics n Ant extra credit problem due today n Extra lab check-off times íMonday 12:30-4:20 íTuesday 12:00-2:00 n All labs must be done by Tuesday 2:00pm n Review session Monday 4:30 pm here n Final Exam Wednesday 2:30 pm here u Today n Computer Organization Overview íWhere some of the things we’ve learned fit in n Review n Evaluation: leave last min for this

2 CSE370, Lecture 26 central processing unit (CPU) instruction unit – instruction fetch and interpretation FSM execution unit – functional units and registers address read/write data Processor Memory System Structure of a computer u Block diagram view control signals data conditions Data PathControl

3 CSE370, Lecture 26 LD asserted during a lo-to-hi clock transition loads new data into FFs OE asserted causes FF state to be connected to output pins; otherwise they are left unconnected (high impedance) OE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD D7 D6 D5 D4 D3 D2 D1 D0 CLK Registers u Selectively loaded – EN or LD input u Output enable – OE input u Multiple registers – group 4 or 8 in parallel

4 CSE370, Lecture 26 Instruction sequencing u Example – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz) u Step 1: get the ADD instruction from memory into an instruction register (IR) u Step 2: decode instruction n instruction in IR has the code of an ADD instruction n register indices used to generate output enables for registers Rx and Ry n register index used to generate load signal for register Rz u Step 3: execute instruction n enable Rx and Ry output and direct to ALU n setup ALU to perform ADD operation n direct result to Rz so that it can be loaded into register

5 CSE370, Lecture 26 Instruction types u Data manipulation n add, subtract n increment, decrement n multiply n shift, rotate n immediate operands u Data staging n load/store data to/from memory n register-to-register move u Control n conditional/unconditional branches in program flow n subroutine call and return

6 CSE370, Lecture 26 Elements of the control unit (aka instruction unit) u Standard FSM elements n state register n next-state logic n output logic (datapath/control signalling) n Moore or synchronous Mealy machine to avoid loops unbroken by FF u Plus additional "control" registers n instruction register (IR) n program counter (PC) u Inputs/outputs n outputs control elements of data path n inputs from data path used to alter flow of program (test if zero)

7 CSE370, Lecture 26 Reset Initialize Machine Register- to-Register Branch Not Taken Branch Taken Instruction execution u Control state diagram (for each diagram) n reset n fetch instruction n decode n execute u Instructions partitioned into three classes n branch n load/store n register-to-register u Different sequence through diagram for each instruction type Init Fetch Instr. Execute Instr. Load/ Store Branch Incr. PC

8 CSE370, Lecture 26 Cin Ain Bin Sum Cout FA HA Ain Bin Sum Cin Cout HA Data path (hierarchy) u Arithmetic circuits constructed in hierarchical and iterative fashion n each bit in datapath is functionally identical n 4-bit, 8-bit, 16-bit, 32-bit, 64-bit datapaths

9 CSE370, Lecture AB SZN Operation 16 Data path (ALU) u ALU block diagram n input: data and operation to perform n output: result of operation and status information

10 CSE370, Lecture Z N OP 16 ACREG 16 Data path (ALU + registers) u Accumulator n special register n one of the inputs to ALU n output of ALU stored back in accumulator u One-address instructions n operation and address of one operand n other operand and destination is accumulator register n AC  AC op Mem[addr] n "single address instructions” (AC implicit operand) u Multiple registers n part of instruction used to choose register operands

11 CSE370, Lecture 26 2 bits wide 1 bit wide Data path (bit-slice) u Bit-slice concept – iterate to build n-bit wide datapaths CO CIALU AC R0 from memory rs rt rd CO ALU AC R0 from memory rs rt rd CIALU AC R0 from memory rs rt rd

12 CSE370, Lecture 26 Instruction path u Program counter n keeps track of program execution n address of next instruction to read from memory n may have auto-increment feature or use ALU u Instruction register n current instruction n includes ALU operation and address of operand n also holds target of jump instruction n immediate operands u Relationship to data path n PC may be incremented through ALU n contents of IR may also be required as input to ALU

13 CSE370, Lecture 26 Data path (memory interface) u Memory n separate data and instruction memory (Harvard architecture) ítwo address busses, two data busses n single combined memory (Princeton architecture) ísingle address bus, single data bus u Separate memory n ALU output goes to data memory input n register input from data memory output n data memory address from instruction register n instruction register from instruction memory output n instruction memory address from program counter u Single memory n address from PC or IR n memory output to instruction and data registers n memory input from ALU output

14 CSE370, Lecture Z N OP 8 ACREG 16 load path store path Data Memory (16-bit words) 16 OP 16 PCIR 16 data addr rd wr MARControl FSM Block diagram of processor u Register transfer view of Princeton architecture n which register outputs are connected to which register inputs n arrows represent data-flow, other are control signals from control FSM n MAR may be a simple multiplexer rather than separate register n MBR is split in two (REG and IR) n load control for each register

15 CSE370, Lecture 26 Control FSM 16 Z N OP 16 ACREG 16 load path store path Data Memory (16-bit words) 16 OP 16 PCIR 16 data addr rd wr Inst Memory (8-bit words) data addr Block diagram of processor u Register transfer view of Harvard architecture n which register outputs are connected to which register inputs n arrows represent data-flow, other are control signals from control FSM n two MARs (PC and IR) n two MBRs (REG and IR) n load control for each register

16 CSE370, Lecture 26 “Why” take CSE 370 u Required (okay, but let’s talk about why it is required and will be useful for your future) u Most basic building blocks of computer science (0’s and 1’s) u It is important to understand how they are used as baseline for more complex operations (adding, storing, other logic like if/while) u It is good to understand what can be implemented in hardware, and why it is sometimes good to implement certain things in hardware instead of software u Understand how some of the technology you interact with on daily basis (memory stick, vending machine, etc) at the hardware logic level. u Knowledge gained in this course is used directly in industry/research

17 CSE370, Lecture 26 What you should know u Combinational logic basics n Binary/hex/decimal numbers n Ones and twos complement arithmetic n Truth tables n Boolean algebra n Basic logic gates n Schematic diagrams n Timing diagrams n de Morgan's theorem n AND/OR to NAND/NOR logic conversion n K-maps (up to 4 variables), logic minimization, don't cares n SOP, POS n Minterm and maxterm expansions (canonical, minimized) I like Pink and Blue but not Yellow…

18 CSE370, Lecture 26 u Combinational logic applications n Combinational design íInput/output encoding íTruth table íK-map íBoolean equation íSchematics n Multiplexers/demultiplexers n PLAs/PALs n ROMs n Adders ???? What you should know

19 CSE370, Lecture 26 u Sequential logic building blocks n Latches (R-S and D) n Flip-flops (D and T) n Latch and flip-flop timing (setup/hold time, prop delay) n Timing diagrams n Asynchronous inputs and metastability n Registers Remember that the last number was 1 What you should know

20 CSE370, Lecture 26 What you should know u Counters n Timing diagrams n Shift registers n Ring counters n State diagrams and state-transition tables n Counter design procedure 1. Draw a state diagram 2. Draw a state-transition table 3. Encode the next-state functions 4. Implement the design n Self-starting counters 1, 2, 3, 4, …

21 CSE370, Lecture 26 u Finite state machines n Timing diagrams (synchronous FSMs) n Moore versus Mealy versus synchronized/registered Mealy n FSM design procedure 1.State diagram 2.state-transition table 3. State minimization 4. State encoding 5. Next-state logic minimization 6. Implement the design n State minimization n One-hot / output-oriented encoding n State partitioning n FSM design guidelines íSeparate datapath and control What you should know (Final exam focus is here though exam is cumulative) Food! start The last coin was 5cents and already had 10cents deposited so let’s pop out a coffee

22 CSE370, Lecture 26 u Finite state machines and Verilog n Understanding simple Verilog n Expressing Moore and Mealy machines in sequential Verilog n Understanding Verilog descriptions of finite state machines expressed in standard stylized formats u Other n Pipelining and Retiming What you should know (Final exam focus is here though exam is cumulative)

23 CSE370, Lecture 26 Final exam logistics u 2:30 – 4:20 (1 hour and 45 minutes long) u Materials: cumulative but more focus on later material HW7, HW8. u Closed book/notes, no calculator u Scratch papers provided u Just have your pencil/pen and eraser u Raise hand for questions (don’t walk to get help)

24 CSE370, Lecture 26 Thank you Thank you for making teaching this course fun I hope you enjoyed the course Send me an or drop in for questions about CSE, etc. Good luck on your final exams!