US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University1 CSC Muon Trigger On Detector Components B. Paul Padley Rice University June, 2002

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University2 CMS Endcap Muon System 3 or 4 stations Each CSC chamber has six planes: 1.Radial cathode strips for precision muon position and bend direction measurement 2.Anode wires for timing (bunch ID) and non-bend position measurement There is also a RPC system overlapping the CSC’s to provide a redundant trigger

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University3 CSC Muon Triggering   Trigger primitives are wire and strip segments Wires give 25ns bunch crossing Strips give precision  information Link trigger primitives into tracks Assign p T, , and  Send highest quality tracks to Global L1

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University4 Trigger requirements Trigger requirements Cathode LCT Identify cathode track segment. P t trigger based on angle of LCT For P t threshold of GeV requires  p/p < 30% (in order to limit single muon trigger rate in Level-1 to a few KHz) Track hits must be located to within ½ strip width in each chamber layer Anode LCT Form anode track segment. Tag bunch crossing of track segment with  92 % efficiency per chamber

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University5 EMU “Trigger” Cards Anode LCT Card (ALCT) Sits on Chamber Receives Anode Front End Board discriminator signals Finds eta coordinate of two best track stubs and quality Sends to Trigger Motherboard Trigger Motherboard (TMB) Receives ALCT info Receives Cathode Front End Board discriminator Signals Finds location, bend angle and quality of two best cathode track stubs Correlates Anode and Cathode LCT’s Sends to Port Card (MPC)

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University6 EMU “Trigger” Cards Cont’d EMU Clock and Control Board (CCB) Receives Clock and Control signals (such as L1accept, reset…) from Trigger Timing and Control system Redistributes these signals on the custom backplane. RPC Interface Module (RIM) Transition module that receives RPC trigger information Could be used in TMB to eliminate ghosts (if they are a problem).

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University7 Endcap Muon Trigger Primitive Generation CSC CFEB ALCT 1 of 24 CFEB 1 of 2 LVDB 1 of 5 Anode Front-end Board Cathode Front-end Board Anode LCT Board MPCMPC DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB CCBCCB CONTROLLERCONTROLLER Peripheral Crate on iron disk Trigger-Timing-Control Muon Sector Receiver Lev-1 Trigger Trig Motherboard DAQ Motherboard Clock Control Board Optical link In underground counting room On detector

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University8 Peripheral Crate MPCMPC DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB CCBCCB CONTROLLERCONTROLLER Only “on detector” “Trigger” board is the Muon Port Card (MPC) It accepts ALCT/CLCT pairs from each TMB Selects the best 3 and sends to counting room. Board# per crate Responsibility VME Cont.1OSU TMB/ CLCT 9UCLA DMB9OSU Clock and Control Board 1Rice Muon Port Card 1Rice There are 48 peripheral crates in the Endcap Muon system

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University9 CSC Sectors Data Mapping

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University10 Strip FE cards Wire FE cards Muon Port Card (Rice) MPC Sector Receiver/ Processor (U. Florida) OPTICAL SR/SP SP CSC Muon Sorter (Rice) Global  Trigger DTRPC FE Global L1 2  / chamber 3  / port card 3  / sector 44 44 44 44 LCT Trigger Motherboard (UCLA) Wire LCT card In counting house TMB LCT RPC Interface Module RIM On-Chamber Trigger Primitives 3-D Track-Finding and Measurement Combination of all 3 Muon Systems CSC Muon Trigger Scheme

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University11 Port Card Sector ReceiverSector Processor OPTICAL SR/SP CSC Muon Sorter CFE Anode LCT MPC ResponsibilitiesResponsibilities Cathode Front-End Anode Front-End Cathode LCT/ Motherboard/ RPC TMB LCT RPC in. Global  Trigger DTRPC Global L1 USCMS Trigger/DAQ USCMS Endcap Muon Vienna Rice Florida Rice OSU CMU UCLA Rice /UCLA Clock & Control1 Clock & Control2 Rice AFE Also: Backplanes - Florida controllers, crates, power supplies, cables

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University12 Current Project Status Trigger primitives are formally part of Endcap Muon project ALCT 384 channel version, in production 672 and 288 channel versions – pre-production prototypes being evaluated CLCT/TMB – 17 prototypes made – 3 debugged and being evaluated First Track Finder system (TRIDAS) prototyped successfully in ‘00 Also, trigger part of CMS OO simulation package was developed Some hardware modifications were desired: Decrease latency Implement DAQ diagnostic readout Currently Building 2 nd prototypes of system

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University13 Technical Issues Addressed with Second Prototypes Level 1 trigger latency Front-end buffer size is limited (tracking, pre-radiators) Track Finder must deliver muons to GMT by 79 crossings (1975 ns) after muon collision Prototype 1 (including trigger primitive electronics) was too slow – some surprises were encountered, e.g. Channel-Link latency about 100 ns ( x5 places used) How to reach requirement is being incorporated in new design: Optimize data transfer protocols between boards Decrease some bit counts Faster FPGA chips (often 80 MHz versus 40 MHz) Improved FPGA algorithms

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University14 Optical Link Radiation Tests Three serializers: up to 270 kRad TID. No permanent damage or SEU Two Finisar optical modules: No errors up to 70 kRad. Failed at ~70kRad (well above ~10 kRad TID inner CSC dose for 10 years) -- Rice

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University15 Muon Port Card Prototype 1 Optical links Main FPGA on Daughter Card VME Interface

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University16 VME J1 CONNECTOR CUSTOM PERIPHERAL BACKPLANE 9U x 400 MM BOARD FINISAR FTRJ OPTICAL TRANSCEIVERS TLK2501 SERIALIZERS CCB INTERFACE SORTING LOGIC INPUT AND OUTPUT FIFO VME INTERFACE 3 OPTICAL CABLES TO SECTOR PROCESSOR TMB_1 TMB_2 TMB_3 TMB_4 TMB_5 TMB_6 TMB_7 TMB_8 TMB_9 SER OPTO SN74GTLP18612 GTLP TRANSCEIVERS FPGA CCB UCLA MEZZANINE CARD (XCV600E) New MPC Design (Rice)

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University17 New Peripheral Backplane Bit 3 VME/PCI interface VME Display 3U VME A24D16 Custom Backplane

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University18 New Port Card Board is partially stuffed We are adding components and then testing, iteratively VME JTAG Input/output FIFO’s Sorting Logic Finisar optical transceiver (1 of 3) TLK2501 (1 of 3) Mezzanine card with PLD (PLD is on other side) Custom backplane connector VME connector Breadboard area (always prudent)

US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University19 PersonnelPersonnel Professors Jay Hauser (UCLA), Paul Padley (Rice) Postdocs Martin Von der Mey (UCLA), TBA (Rice) Students Greg Pawloski (Rice) Engineers JK (UCLA), Mike Matveev (Rice), Ted Nussbaum (Rice)