4H-SIC DMOSFET AND SILICON CARBIDE ACCUMULATION-MODE LATERALLY DIFFUSED MOSFET Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 1

SiC excellent electrical and thermal properties. only semiconductor material besides Si on which a thermal oxide can be grown Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 2

Materials PropertySiSiC-4HGaN Band Gap (eV) Critical Field 106 V/cm Electron Mobility (cm2/V-sec) Electron Saturation Velocity (106 cm/sec) Thermal Conductivity (Watts/cm2 K) Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 3

Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 4

STRUCTURE OF POWER MOSFET: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 5

STRUCTURE OF 4H-SIC DMOSFET : Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 6

STRUCTURE: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 7 The MOS channel length is defined by the p- well and n+ implants, and can range from 0.5 μm to 1.5 μm. Electron flow : n+ source - inversion layer - implanted p-well -JFET region - lightly doped n- drift region - drain.

STRUCTURE OF Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 8 The blocking voltage of the MOSFET is determined by the doping concentration of the n- epilayer. For 1200 V devices, an epilayer with a doping concentration of 6x10 15 cm-3 and a thickness of 12 μm can be used. A thermally grown oxide layer is typically used as gate dielectric due to its repeatability and stability.

STRUCTURE Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 9 Typically, the gate oxide is nitrided in NO or N2O to reduce MOS interface state density, which improves the transconductance of the MOSFET.

TRANSFER CHARACTERISTICS: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 10

OUTPUT CHARACTERISTICS: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 11

STRUCTURE OF SiC AMLDM: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 12

STRUCTURE: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE A thin n-channel region (accumulation-layer) below the gate oxide. Normally off device with the entire drain voltage supported by the p/n-drift region. Support high forward blocking voltages at zero gate bias with low leakage currents. 13

STRUCTURE: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE A low resistance path for the electron current flow from the source to the drain can be achieved. This structure utilizes the buried p-well region as a shield to the influence of a high SiC bulk electric filed on the gate oxide. Removes the effect of interface quality on the channel mobility. 14

EFECT OF ACCUMULATION LAYER THICKNESS ON OPERATING VOLTAGE AND SPECIFIC ON RESISTANCE: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 15

TRANSFER CHARACTERISTICS: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 16

OUTPUT CHARACTERISTICS: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 17

OFF STATE CHARCATERISTICS: Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE 18

Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics & Drives Dept. of EEE THANK YOU 19