STRJ-WG1 December 12,2000 - 1 Design ITWG Mtg. ~ Toward the ITRS 2001 Design Chapter and SoC Chapter ~ STRJ-WG1 Dec 2000.

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Presentation transcript:

STRJ-WG1 December 12, Design ITWG Mtg. ~ Toward the ITRS 2001 Design Chapter and SoC Chapter ~ STRJ-WG1 Dec 2000

STRJ-WG1 December 12, Meeting agenda ◆ Taiwan ITRS Meeting Report ◆ Analog Roadmap presentation from Europe ◆ Discussion and Planning on ITRS2001 ◆ Misc. - Generic info on ITRS1999 update - Important direction for ITRS etc. - sketch a new analog roadmap Ralf Brederlon will present - “SoC Chapter” --- “System Drivers” proposal from US - “Design Chapter” --- New contents to be added, etc. - International cooperation, 2001 meeting schedule, and etc.

STRJ-WG1 December 12, Scenario for SoC Design Productivity (ITRS 1999 update - Design Chapter)

STRJ-WG1 December 12, Scenario for SoC Design Productivity (ITRS 1999 update - Design Chapter)

STRJ-WG1 December 12, Is there any important info from Taiwan ITRS Meeting ? Memo

STRJ-WG1 December 12, ◆ Analog Roadmap presentation from Europe

STRJ-WG1 December 12, ◆ Discussion and Planning on ITRS2001

STRJ-WG1 December 12, ◇ SoC Chapter in ITRS 1999 〇 What is a System-On-a-Chip? 〇 Process Requirements for Advanced Technologies 〇 Packaging Considerations 〇 Test for SoC - Main Emphasis - Cost-Based Designs - Programmable versus Hard-Wired - System-On-a-Chip Packaging - RF and Mixed-Signal Packaging - Multi-Chip Packages, Multi-Chip Modules, and System-In-a-Packaging (Tables) Table 8 Major Characteristics and Emphasis of SoC Classifications Table 9 Example of Circuit Fabrics Table 10 Example Applications of Programmable and Nonprogrammable SoCs Table 11 Added Process Complexity for SoC Technologies Table 12a SoC Test Technology Requirements - Near Term Table 12b SoC Test Technology Requirements - Long Term

STRJ-WG1 December 12, ◇ SoC/System Drivers Chapter in ITRS 2001 ◇ Design Chapter in ITRS 2001 〇 Defining the major system types (e.g., high-volume/low volume MPU, ASIC, and SOC) 〇 Features and profiles for each typical type “SoC” 〇 Comprehensive analysis for required technologies for each type of “SoC”, if those are specific to types ( Just a Strawman ! ) 〇 Entire design methodology Roadmap from System level to Mask making 〇 High-lighting IP reuse methodology Roadmap 〇 Design Productivity scenario for each typical type “SoC”

STRJ-WG1 December 12, ◇ SoC/System Drivers Chapter in ITRS 2001 ◇ Design Chapter in ITRS 2001 〇 Updates from ITRS 1999 Design Chapter (e.g., Design Complexity, Design Difficult Challenges ) 〇 Analog/RF roadmap tables with descriptions 〇 Low Power roadmap table with description ( Just a Strawman ! ) 〇 Detail analysis on some most difficult issues in design (e.g., Analog macro design, 3D extraction, Power, Noise, Signal Integrity, System simulation, Formal Checking, Chip Test, Diagnostics ) 〇 Need more Roadmap tables !

STRJ-WG1 December 12, ◇ What STRJ/WG1 Plans for STRJ2001 〇 In STRJ1999 We focused on - Design Productivity Roadmap - Low Power Roadmap - Deep Sub-micron technology requirements Roadmap 〇 Candidates for STRJ 2001 ( Now, under discussions ) - System level design (including S/W design) Roadmap - Revise Design Productivity Roadmap table - Investigate “Jisso” related technology requirements and make some Roadmap - Deepen Joint activities with other TWGs

STRJ-WG1 December 12, ◆ Misc. - Another meeting in addition to 3/Year ITRS ITWG Mtg. - Participation from Taiwan and Korea - Any good idea to share task among US, Europe and Japan - Need Design ITWG chairman - Cross cut items (eg. Interconnect, Transistor) - etc.