Documentation Standards (contd.) ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Documentation Standards (contd.)

Previous… Block diagram Schematics Diagram Gate symbols Signal names Active levels for signal names/pins

Bubble-to-Bubble Logic Design Purpose : To make it easy to understand the function of the Logic circuit by choosing appropriate logic symbols and signal names including active-level designators. FAIL_L FAIL_L ERROR ERROR OVERFLOW_L OVERFLOW_L

Bubble-to-Bubble Logic Design Rules - The SIGNAL NAME of the output signal of a logic device should match the active level of the device’s output pin. Active-low if the device symbol has an inversion bubble, active-high if not. - If the active level of an input signal is the same as that of the device’s input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is asserted. Most common case. - If the active level of an input signal is the opposite of that of the input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is negated. Should be avoided. ERROR ERROR OVERFLOW HALT_L READY READY_L ERROR REQUEST REQUEST FAIL_L ERROR ENABLE_L ENABLE OVERFLOW_L

Examples (Wakerly pp352)

Another example

Drawing Layouts Inputs to the left/top, outputs to the right/bottom. Signals flow from left to right (or top to bottom). Signal paths should be connected. Broken signal paths should be flagged to indicate the source or destination and direction. Crossing lines/Connected lines (T-type connection) Multiple pages schematics: - Flat Structure. - Hierarchical Structure.

Drawing Layout: Flat schematic structure 4,6 5

Hierarchical schematic structure

Some rules to avoid common errors Use exactly the same name for same signal. Use different names for different signals. (especially cross pages) Use appropriate active levels for signal names Use “T” convention for connected lines.

Buses Example: Figure 6-16, pp359 (next slide) DATA[0-7] DATA5 DATA6 Buses should be named : DATA[0:7], CONTROL A bus name may use brackets and a colon to denote a range Buses are drawn with thicker lines than ordinary signals. Individual signals are put into or pulled out of the bus by connecting an ordinary signal line to the bus and writing the signal name. (A special connection dot is often used.) A signal extracted from a bus should be named Inter-page signal/Bus Flags : Uni-direction Bi-direction Example: Figure 6-16, pp359 (next slide)

Logic Diagram to Schematic Diagram Logic Diagram Schematic Diagram Bubble-to-Bubble Logic IC-Type-Logic Family Pin numbers- Pin Diagram Reference designator- Unit Number 74LS04 74LS00 1 2 1 A A_L 3 74LS00 U2 2 F 10 F U1 8 3 4 B B_L 9 74LS00 4 U1 6 74LS04 U2 5 U1

Complete schematic diagram IC types: a part number identifying the IC that performs a given logic function. Also defines the device’s logic family and speed. E.g.. 74HCT00, 74LS00 Reference designators: a particular instance of that IC type installed in the system. U1,U2… Pin numbers: used to locate individual logic signal numbers on its pins.

Example schematic

Dual-inline packages (74 series)

Pinouts for SSI ICs in standard dual-inline packages (pp. 329) Small elements in 74x03 indicate an open-drain or open-collector output

Combinational SSI devices (Contd.) Small elements in 74x14 hysteresis

Combinational SSI devices (Contd.) Small elements in 74x266 indicate an open-drain or open-collector output

Next… Circuit Timing