Agata Week – LNL 14 November 2007 LLP ATCA Carrier Status M. Bellato on behalf of the LLP Carrier Working Group

Agata Week – LNL 14 November 2007 Agata Front-end Model

Agata Week – LNL 14 November 2007

Clock Distribution From GTS Tree

Agata Week – LNL 14 November 2007 MGT Clocking Layout RocketIO 101 RocketIO 101 MUX RocketIO 102 RocketIO 102 MUX RocketIO 103 RocketIO 103 MUX RocketIO 105 RocketIO 105 MUX MGTclk M34/N34 MGTclk M34/N34 MGTclk AP28/AP29 MGTclk AP28/AP29 RocketIO 106 RocketIO 106 MUX RocketIO 109 RocketIO 109 MUX RocketIO 110 RocketIO 110 MUX RocketIO 112 RocketIO 112 MUX RocketIO 113 RocketIO 113 MUX MGTclk AP3/AP4 MGTclk AP3/AP4 MGTclk J1/K1 MGTclk J1/K1 RocketIO 114 RocketIO 114 MUX ATCA FABRIC CH1-CH2 ATCA FABRIC CH3-CH4 ATCA FABRIC CH5-CH6 ATCA FABRIC CH7-CH8 ATCA FABRIC CH9-CH10 ATCA FABRIC CH11-CH12 USER SFP TRANSCEIVER RTM PCI EXPRESS LANE0 RTM PCI EXPRESS LANE5 RTM PCI EXPRESS LANE1 RTM PCI EXPRESS LANE2 100  250MHz PCI Express JITTER ATTENUATOR 100  250MHz PCI Express JITTER ATTENUATOR 200MHz GTS Clock 200MHz GTS Clock (**) The ATCA FABRIC channels are routed from CHANNEL1 to CHANNEL12 by switches (***) User SFP could be used as 1GEnet or PCIExpress DAQ without FABRIC RTM PCI EXPRESS LANE3 RTM PCI EXPRESS LANE4 ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB INSPECTION PADS 100MHz GTS Clock 100MHz GTS Clock OPTICAL SFP OPTICAL SFP INSPECTION PADS LOCAL 100MHz (EPSON ) LOCAL 100MHz (EPSON ) PHASE LOCKED MGT clocking layout

Agata Week – LNL 14 November V DC ENABLE P3V3-5A 16.5W MEZZANINE 1 MEZZANINE 2 MEZZANINE 3 MEZZANINE 4 MAIN BOARD P3V3-7A 23.1W MAIN BOARD P2V5-7A 17.5W FPGAs CORE P1V2-7A 8.4W FPGA MGT P1V2-4A 4.8W P2V5-1.5A P1V8-0.5A PROMS VCCAUX Fpga 1 VCCAUX MGT P2V5-1.5AVCCAUX Fpga 2 P1V2-0.5A VTTTXs P1V2-0.5AVTTRXs MGT BUFFERSP1V8-6A 10.8W P12V-14.7A 176.7(160.6)W P3V3-5A 16.5W M48V-4.0A 194.4(176.7)W DC-DC Efficency is estimated at least 90% ATC210 (210W) P3V3_BOOT 4x LTM W 6x LTM W P5V0-6A 30W Carrier Power Supply

Agata Week – LNL 14 November M x 18 true dual port 100/200 MHZ 800Mb/s LVDS streaming on data channels Equalized and filtered distribution of 200MHZ GTS clock 1 PCI Express/ GE optical link 15 x Full mesh connectivity on the backplane Pervasive I2C bus for slow controls 200W power supply Multiple options for data readout Carrier main features

Agata Week – LNL 14 November 2007 Pre-placement Attempt (as of nov. 06)

Agata Week – LNL 14 November 2007 Pre-placement Attempt (as of nov. 06)

Agata Week – LNL 14 November 2007 Final Placement

Agata Week – LNL 14 November 2007 Final Routing (as of april 07)

Agata Week – LNL 14 November 2007 Power and Signal Integrity Simulations

Agata Week – LNL 14 November 2007 Example Resonant mode between L6pwr/L11gnd

Agata Week – LNL 14 November 2007 Prototype (as of july 07)

Agata Week – LNL 14 November 2007

Started in august still going on >18 different tests Jtag chains FPGAs configurations Power distribution I2C control chains 200 MHz Clock distribution Microprocessor Sdram mems Flash mem Dual port ram PLL PCI Express optical link Fast Ethernet switch + PHY’s MII connections Backplane 2.5 Gb/s serial links Mezzanine connections 800 Mb/s LVDS lanes Trigger distribution Master/slave functionality Tests Campaign

Agata Week – LNL 14 November 2007

CH-15 Eye Diagram with Equalization

Agata Week – LNL 14 November 2007

Via hole should be symmetric wrt solder balls

Agata Week – LNL 14 November 2007 ChipSync™ FPGA Fabric Data width of of 2, 3, 4, 5, 6, 7, 8, 10 BUFIO CLKCLKDIV ISERDES BUFR Clk Div Clk Div Serdes Advantage

Agata Week – LNL 14 November 2007 ChipSync™ FPGA Fabric ISERDES CLK DATA INC/DEC IDELAY State Machin e IDELAY CNTRL MHz (calibration clk) 64 delay elements of ~ 70 to 89 ps each Calibration clock can be internal or external Bit Alignment

Agata Week – LNL 14 November 2007 INCDEC State Machine State Machine Clock Sampling Phase Adjust

Agata Week – LNL 14 November 2007 ChipSync FPGA Fabric ISERDES BITSLIP State Machine State Machine CLK DATA Up to 10-bit bitslip pattern for any length training patterns Word Alignment

Agata Week – LNL 14 November State Machine State Machine Bitslip 1 Bitslip 2 Bitslip 3 DATA1 DATA2 DATA3 Word Alignment Animation

Agata Week – LNL 14 November 2007

Eye Diagram of LVDS pins

Agata Week – LNL 14 November 2007 S-parameters of a lvds pair from Mictor conns to main FPGA through full wave EM solver Encrypted Hspice model of lvds25ext pad from Xilinx Hspice simulation Spice Verification

Agata Week – LNL 14 November 2007 Hspice result

Agata Week – LNL 14 November 2007 Int *ATCA0 = 0xfe001000; // DPRAM on board 0 Int *ATCA1 = 0xfe002000; // DPRAM on board 1 …. Fragment0 = memcpy(buffer0, ATCA0); Fragment1= memcpy(buffer1, ATCA1); PCI Express Readout Test

Agata Week – LNL 14 November 2007 Tests ongoing –Excessive noise on DC/DC converters - not suitable for high speed operation –Central reset manager missing –Some errors on components footprints –90% completed Modifications already ongoing at CERN –The layout will be frozen until the end of tests Procurement of components for 2 pre- production boards ongoing Status

Agata Week – LNL 14 November 2007 Expected layout completion : end of Dec 07 Signal integrity analysis  end of Jan 08 2 x PCB manufacturing : Feb 08 2 x PCB assembly : Mar 08 2 x Board tests  Apr 08 Schedule