PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} P37X Non-Pipelined Datapath - Spring 2006

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} ALU1: 0000 Names: ______________________________ CSE372 Lab 3, part a

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} ALU2: 0001

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} TRAP: 0010

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} RTT: 0011

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} JUMP: 0100

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} JUMPR: 0101

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} JSR: 0110

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} JSRR: 0111

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} BR: 1000

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} CONST: 1001

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} INC: 1010

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} LEA: 1011

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} LDR: 1100

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} STR: 1101

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} LD: 1110

PC Memory 2 16 by 16 bit Reg. File ALUALU SEXT 16 I[5:0] I[7:0] 8 6 Controller +1 Rd1 Rd2 Wr WE Out1 In Out2 I Memory 2 16 by 16 bit 16 WE ZEXT 16 I[11:0] 12 SEXT 16 I[8:0] 9 InData Addr I[8:6] 3’b111 Zero 16 I[11:9] I[5:3] I[11:9] I[8:6] I[15:12] I[11:9] Out 16 BR Logic 4’b0100 {I[12],I[2:0]} ST: 1111