CMX Collection file for current diagrams 30-Apr-2014.

Slides:



Advertisements
Similar presentations
GOLD Generic Opto Link Demonstrator Uli Schäfer 1.
Advertisements

Uli Schäfer JEM Status and Test Results Hardware status JEM0 Hardware status JEM1 RAL test results.
CPT Week, Nov 2003, B. Paul Padley, Rice University1 CSC Trigger Status, MPC and Sorter B. Paul Padley Rice University November 2003.
Uli Schäfer JEM Status and plans Hardware status JEM0 Hardware status JEM1 Plans.
ALICE Trigger System Features Overall layout Central Trigger Processor Local Trigger Unit Software Current status On behalf of ALICE collaboration:D. Evans,
GOLD Generic Opto Link Demonstrator Uli Schäfer 1.
Phase-0 topological processor Uli Schäfer Johannes Gutenberg-Universität Mainz Uli Schäfer 1.
Level-1 Topology Processor for Phase 0/1 - Hardware Studies and Plans - Uli Schäfer Johannes Gutenberg-Universität Mainz Uli Schäfer 1.
Uli Schäfer 1 (Not just) Backplane transmission options.
S. Silverstein For ATLAS TDAQ Level-1 Trigger updates for Phase 1.
Samuel Silverstein Stockholm University L1Calo upgrade hardware planning + Overview of current concept + Recent work, results.
Uli Schäfer 1 JEM: Status and plans Pre-Production modules Status Plans.
Uli Schäfer 1 JEM: Status and plans JEM1.2 Status Test results Plans.
Uli Schäfer 1 JEM1: Status and plans JEM1.1 Status Plans.
S. Silverstein For ATLAS TDAQ Level-1 Trigger upgrade for Phase 1.
Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans.
Uli Schäfer 1 (Not just) Backplane transmission options.
Digital CFEB Prototype Plans 1 B. Bylsma, CSC Upgrade Workshop, Ohio State Univ., April 23-24, 2010 Ben Bylsma The Ohio State University.
C-Card and MMFE using the BNL Peak Finding ASIC (VMM1) Ken Johns, Joel Steinberg, Jason Veatch, Venkat Kaushik (U. Arizona)
Status and planning of the CMX Philippe Laurens for the MSU group Level-1 Calorimeter Trigger General Meeting, CERN May 24, 2012.
Huazhong Normal University (CCNU) Dong Wang.  Introduction to the Scalable Readout System  MRPC Readout Specification  Application of the SRS to CMB-MRPC.
PCIe Mezzanine Carrier Pablo Alvarez BE/CO. Functional Specifications External Interfaces User (application) FPGA System FPGA Memory blocks Mezzanine.
20/10/2008A. Alici - ALICE TOF Festival1 Electronics and data acquisition of the ALICE TOF detector A.Alici University and INFN, Bologna.
Preliminary Design Review: Hub Implementation Dan Edmunds, Wade Fisher, Yuri Ermoline, Philippe Laurens Michigan State University 01-Oct-2014.
CMX (Common Merger eXtension module) Y. Ermoline for CMX collaboration Preliminary Design Review, Stockholm, 29 June 2011.
Topology System Uli Schäfer 1 B.Bauß, V.Büscher, W.Ji, U.Schäfer, A.Reiß, E.Simioni, S.Tapprogge, V.Wenzel.
Atlas L1Calo CMX Card CMX is upgrade of CMM with higher capacity 1)Inputs from JEM or CPM modules – 40 → 160Mbps (400 signals) 2)Crate CMX to System CMX.
SRS Readout System for VMM2 Sorin Martoiu, IFIN-HH (RO)
L1Topo Status & Plans Uli Schäfer 1 B.Bauß, V.Büscher, W.Ji, S.Krause, S.Moritz, U.Schäfer, A.Reiß, E.Simioni, S.Tapprogge, V.Wenzel.
Understanding Data Acquisition System for N- XYTER.
June 29th 2005Ph. BUSSON LLR Ecole polytechnique, Palaiseau1 Plans for a new TCC for the endcaps Characteristics: reminder Preliminary list of tasks and.
Leo Greiner IPHC DAQ Readout for the PIXEL detector for the Heavy Flavor Tracker upgrade at STAR.
Status of Global Trigger Global Muon Trigger Sept 2001 Vienna CMS-group presented by A.Taurok.
CPT Week, April 2001Darin Acosta1 Status of the Next Generation CSC Track-Finder D.Acosta University of Florida.
Uli Schäfer 1 JEM Status and plans Hardware -JEM1 -Status Firmware -Algorithms -Status Plans.
CMS Global Calorimeter Trigger Hardware Design 21/9/06.
CMX status and plans Yuri Ermoline for the MSU group Level-1 Calorimeter Trigger Joint Meeting CERN, October 2012,
Wilco Vink 1 Outline Optical station Vertex processor board Output board Latency.
CMX status Yuri Ermoline for the MSU group Mini-TDAQ week, CERN, 9-11 July 2012,
Status and planning of the CMX Wojtek Fedorko for the MSU group TDAQ Week, CERN April , 2012.
CMX Hardware Status Chip Brock, Dan Edmunds, Philippe Yuri Ermoline, Duc Bao Wojciech UBC Michigan State University 25-Oct-2013.
Leo Greiner PIXEL Hardware meeting HFT PIXEL detector LVDS Data Path Testing.
CMX Hardware Overview Chip Brock, Dan Edmunds, Philippe Yuri Wojciech Michigan State University 12-May-2014.
Upgrade to the Read-Out Driver for ATLAS Silicon Detectors Atlas Wisconsin/LBNL Group John Joseph March 21 st 2007 ATLAS Pixel B-Layer Upgrade Workshop.
ATLAS Trigger / current L1Calo Uli Schäfer 1 Jet/Energy module calo µ CTP L1.
MTF7 hardware status Alex Madorsky for UF group. Muon Trigger structure rework A. Madorsky2 Endcap TF Overlap TFBarrel TF - Overlap TF is now.
CMX Hardware Overview Chip Brock, Dan Edmunds, Philippe Yuri Wojciech Michigan State University 19-May-2014.
Costas Foudas, The Tracker Interface to TCS, The CMS Silicon Tracker FED Crates What goes in the FED Crates ? What do we do about the VME controller.
Samuel Silverstein Stockholm University CMM++ firmware development Backplane formats (update) CMM++ firmware.
FEC electronicsRD-51 mini week, CERN, Sept Towards the scalable readout system: FEC electronics for APV25, AFTER and Timepix J.
Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.
Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory30 July 2001 CMS Tracker FED CMS Tracker System.
CMX firmware development Pawel Plucinski Stockholm University Stockholm University CMX firmware status G-Link and GTX serializer Clock manager Memory Conclusions.
Control for CTP and LTU boards in Run
VC707 Evaluation Kit Xilinx Virtex-7 In_0 GTX MHz IDELAY 8B/10B Serilizer 7 0 7IDELAY 0=>K28.5 0=>K28.1 D(15:0) K(1:0) 8B/10B IDELAYCTRL LHC_Clk.
Samuel Silverstein, SYSF ATLAS calorimeter trigger upgrade work Overview Upgrade to PreProcessor MCM Topological trigger.
E. Hazen - DTC1 DAQ / Trigger Card for HCAL SLHC Readout E. Hazen - Boston University.
CMX: Update on status and planning Yuri Ermoline, Wojciech Dan Edmunds, Philippe Laurens, Chip Michigan State University 7-Mar-2012.
E. Hazen1 MicroTCA for HCAL and CMS Review / Status E. Hazen - Boston University for the CMS Collaboration.
E. Hazen -- CMS Week HCAL Back-End MicroTCA Upgrade Status E. Hazen Boston University.
10/28/09E. Hazen FNAL Workshop1 HCAL DAQ / Timing / Controls Module Eric Hazen, Shouxiang Wu Boston University.
DAQ / Trigger Card for HCAL SLHC Readout E. Hazen - Boston University
DAQ / Trigger Card for HCAL SLHC Readout E. Hazen - Boston University
ATLAS calorimeter and topological trigger upgrades for Phase 1
E. Hazen - Back-End Report
AMC13 Status Report AMC13 Update.
L1Calo Phase-1 architechure
ALICE Trigger Upgrade CTP and LTU PRR
CMX Status and News - post PRR -
(Not just) Backplane transmission options
Presentation transcript:

CMX Collection file for current diagrams 30-Apr-2014

Board Support FPGA 12x Optic OUT 12x Optic IN SFP DAQ SFP DAQ SFP ROI SFP ROI SFP DAQ SFP DAQ SFP ROI SFP ROI TTC Receiver VME -- TCM Inputs from All 16x JEM or 14x CPM Processors From this crate (400x single ended 2.5V CMOS 160 Mbps) 2x 12-fiber ribbons OUT Optical output From Base Function To L1Topo and/or CMX-Topo (up to 6.4 Gbps) Optical output DAQ &ROI readout From Base Function (2x G-Link or S-Link) CMX Card with Base-CMX functionality only CTP output From Base Function (up to 2x 33x LVDS up to 160 Mbps) 30-Apr-2014 MUXMUX MUXMUX LVDS Transceivers Clock Generator Base Function FPGA Virtex-6 LX550T-FF1759 Base Function FPGA Virtex-6 LX550T-FF x Optic OUT Topo Function FPGA Virtex-6 LX550T-FF1759 Topo Function FPGA Virtex-6 LX550T-FF1759 CAN Bus Monitoring Temp, V & I CAN Bus Monitoring Temp, V & I LVDS Transceivers Test Connector: JTAG, CAN bus & Access Signals VME - - Bus Transceivers System ACE System ACE CAN Bus Compact Flash Card Compact Flash Card MPT LVDS cables From Crate CMX To System CMX (up to 3x 27x LVDS up to 160 Mbps)

Board Support FPGA 12x Optic OUT 12x Optic IN SFP DAQ SFP DAQ SFP ROI SFP ROI SFP DAQ SFP DAQ SFP ROI SFP ROI TTC Receiver VME -- TCM 2x 12-fiber ribbons OUT 3x 12-fiber ribbons IN CMX Card with Base-CMX functionality and TP-CMX capability 30-Apr-2014 MUXMUX MUXMUX LVDS Transceivers Clock Generator Base Function FPGA Virtex-6 LX550T-FF1759 Base Function FPGA Virtex-6 LX550T-FF x Optic OUT Topo Function FPGA Virtex-6 LX550T-FF1759 Topo Function FPGA Virtex-6 LX550T-FF1759 CAN Bus Monitoring Temp, V & I CAN Bus Monitoring Temp, V & I LVDS Transceivers VME - - Bus Transceivers System ACE System ACE CAN Bus Compact Flash Card Compact Flash Card MPT Test Connector: JTAG, CAN bus & Access Signals CTP output From Topo Function (up to 2x 33x LVDS up to 160 Mbps) Inputs from All 16x JEM or 14x CPM Processors From this crate (400x single ended 2.5V CMOS 160 Mbps) LVDS cables From Crate CMX To System CMX (up to 3x 27x LVDS up to 160 Mbps) Optical output DAQ &ROI readout From Base Function (2x G-Link or S-Link) Optical output DAQ &ROI readout From Topo Function (2x G-Link or S-Link) Optical output From Base Function To L1Topo and/or CMX-Topo (up to 6.4 Gbps) Optical input From up to 12 CMXs To CMX-Topo (up to 6.4 Gbps)

IO Banks available on Virtex6 LX550T

CMX IO Bank Assignment for Processor Inputs (using only Inner Columns and exactly two Regional Clocks per Horizontal Row) P03 P02 P01 P00 P15 P14 P13 P12 P10 P11 P08 P09 P06 P07 P04 P Number of Regional Clocks used per IO Bank (2 per row  match for MMCM)

ElectronEnergyJetTau CMX Base FPGA CMX Base FPGA to CTP LVDS Cables to CTP CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA LVDS Cables LVDS Cables LVDS Cables Crate CMXs System CMXs CMX emulation of CMM functionality (no TP involved) 21-May-2014

Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX Crate CMX ElectronEnergyJetTau CMX Base FPGA CMX Base FPGA to CTP LVDS Cables to CTP CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA CMX Base FPGA LVDS Cables LVDS Cables LVDS Cables Optical Patch Panel Optical Patch Panel to CTP L1Topo N x 12 L1topo receives Zero-Suppressed data from all CMXs Up to 24x 12-fiber ribbons 2x12 2x 12-fiber ribbon Crate CMXs System CMXs May-2014 System CMX System CMX System CMX System CMX

Older CMX Diagrams Historical repository Some still valid or may need editing

ElectronEnergyJetTau Base- CMX FPGA Base- CMX FPGA to CTP LVDS Cables to CTP Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA LVDS Cables LVDS Cables LVDS Cables Crate CMXs System CMXs to CTP Standalone Topological Processor Standalone Topological Processor 2. Standalone TP receiving Raw CMX Inputs x 12-fiber ribbons 1 x 12-fiber ribbon

ElectronEnergyJetTau Base- CMX FPGA Base- CMX FPGA to CTP LVDS Cables to CTP Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA LVDS Cables LVDS Cables LVDS Cables Optical Patch Panel Optical Patch Panel TP- CMX FPGA TP- CMX FPGA to CTP TP- CMX FPGA TP- CMX FPGA to CTP Crate CMXs System CMXs One (or more) CMX TP receiving Zero-Suppressed Inputs 1 x 12-fiber ribbon x 12 fiber ribbons 3 x 12-fiber

ElectronEnergyJetTau Base- CMX FPGA Base- CMX FPGA to CTP LVDS Cables to CTP Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA LVDS Cables LVDS Cables LVDS Cables Optical Patch Panel Optical Patch Panel TP- CMX FPGA TP- CMX FPGA to CTP Crate CMXs System CMXs CMX TP & Standalone TP receiving Zero-Suppressed Inputs 2 x 12-fiber ribbon 24 up to 24 x 12-fiber ribbons 3 x 12-fiber to CTP Standalone Topological Processor Standalone Topological Processor N x 12-fiber ribbons

ElectronEnergyJetTau Base- CMX FPGA Base- CMX FPGA to CTP LVDS Cables to CTP Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA LVDS Cables LVDS Cables LVDS Cables Optical Patch Panel Optical Patch Panel TP- CMX FPGA TP- CMX FPGA to CTP Crate CMXs System CMXs CMX TP receiving Zero-Suppressed & Standalone TP raw inputs 2 x 12-fiber ribbon x 12-fiber ribbons 3 x 12-fiber to CTP Standalone Topological Processor Standalone Topological Processor 12 x 12-fiber ribbons

ElectronEnergyJetTau Base- CMX FPGA Base- CMX FPGA to CTP LVDS Cables to CTP Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA Base- CMX FPGA LVDS Cables LVDS Cables Optical Patch Panel Optical Patch Panel TP- CMX FPGA TP- CMX FPGA to CTP Crate CMXs System CMXs Example of TP-CMX FPGA in Crate to System communication 1 x 12-fiber ribbon 4 x 12 fiber ribbons 3 x 12 fibers