Boolean Algebra and Logic Gates EE 240 – Logic Design Chapter 2 Boolean Algebra and Logic Gates Sohaib Majzoub

Logic Functions: Boolean Algebra INVERTER X X’ If X=0 then X’=1 If X=1 then X’=0 A B C=A·B If A=1 AND B=1 then C=1 otherwise C=0 AND OR A B C=A+B If A=1 OR B=1 then C=1 otherwise C=0

Axioms of Boolean Algebra If X ≠ 0 then X = 1 If X ≠ 1 then X = 0 If X = 0 then X’ = 1 If X = 1 then X’ = 0 0 . 0 = 0 1 + 1 = 1 1 . 1 = 1 0 + 0 = 0 0 . 1 = 1 . 0 = 0 0 + 1 = 1 + 0 = 1

Boolean expressions and logic circuits Any Boolean expression can be implemented as a combination of AND, OR, and NOT X = [A’.(C+D)]’+B.E C D C+D A’.(C+D) [A’.(C+D)]’ [A’.(C+D)]’+B.E A’ A B E B.E

Basic Theorems Identity Law Null Element X C=X X 1 C=X X 1 C=1 X C=0 C=X X 1 C=X X·1 = X Null Element X+1 = 1 X 1 C=1 X C=0 X·0 = 0

Basic Theorems: Idempotent Laws X+X = X X C=X X C=X X·X = X

Basic Theorems: Involution Law (X’)’=X B X C=X

Basic Theorems: Laws of Complementarity X+X’ = 1 X X’ C=1 X X’ C=0 X·X’ = 0

Expression Simplification using the Basic Theorems X can be an arbitrarily complex expression. Simplify the following boolean expressions as much as you can using the basic theorems. (A.B’ + D).E + 1 = (A.B’ + D).(A.B’ + D)’ = (A.B + C.D) + (C.D + A) + (A.B + C.D)’ =

Associative Law (X+Y)+Z = X+(Y+Z) X Y Z C

Associative Law (XY)Z = X(YZ) X Y Z C Y Z X C

First Distributive Law X(Y+Z) = XY+XZ

Second Distributive Law X+YZ = (X+Y)(X+Z)

Second Distributive Law (A different proof) (X + Y)(X + Z) = X(X + Z) + Y(X + Z) (using the first distributive law) = XX + XZ + YX + YZ (using the first distributive law) = X + XZ + YX + YZ (using the idempotent law) = X·1 + XZ + YX + YZ (using the operation with 1 law) = X(1 + Z + Y) + YZ (using the first distributive law) = X·1 + YZ (using the operation with 1 law) = X + YZ (using the operation with 1 law)

Distributive Law (Another formula) X.Y + Z.W = (X+Z).(X+W).(Y+Z).(Y+W) X.Y + Z.W.V =(X+Z).(X+W).(X+V).(Y+Z).(Y+W).(Y+V) Proof?

More Theorems Combining Theorem Covering or Absorption Theorem XY + XY’ = X XY + XY’ = X(Y + Y’) = X·1 = X (X + Y)(X + Y’) = X (X + Y)(X + Y’) = XX + XY’ + YX + YY’ = X + X(Y’ + Y) + 0 = X + X·1 = X Covering or Absorption Theorem X + XY = X X(1 + Y) = X·1 = X X(X + Y) = X X(X + Y) = XX + XY = X·1 + XY = X(1 + Y) = X·1 = X

The Consensus Theorem XY + X’Z + YZ = XY + X’Z XY + X’Z + YZ = XY + X’Z + 1·YZ = XY + X’Z + (X + X’)YZ = XY + X’Z + XYZ + X’YZ = XY + XYZ + X’Z + X’YZ = XY(1 + Z) + X’Z(1 + Y) = XY·1 + X’Z·1 = XY + X’Z (X+Y)(X’+Z)(Y+Z) = (X+Y)(X’+Z)

The complement of the sum is equal the product First DeMorgan’s Law (X+Y)’ = X’Y’ X X Y  Z Z Four Different Equivalents of NOR Gate Y  X Y X Y Z Z The complement of the sum is equal the product of the complements.

The complement of the product is equal the sum Second DeMorgan’s Law (XY)’ = X’ + Y’ Z Y X  Z X Y Four Different Equivalents of NAND Gate  X Y X Y Z Z The complement of the product is equal the sum of the complements.

Generalized DeMorgan’s Laws De Morgan’s laws generalize to n variables: (X1 + X2 + X3 + ··· + Xn)’ = X1’X2’X3’ ··· Xn’ (X1X2X3 ··· Xn)’ = X1’ + X2’ + X3’ + ··· + Xn’

DeMorgan’s Law (example) Express the complement f’(w,x,y,z) of the following expression in a simplified form. f(w,x,y,z) = wx(y’z + yz’) f’(w,x,y,z) = w’ + x’ + (y’z +yz’)’ = w’ + x’ + (y’z)’(yz’)’ = w’ + x’ + (y + z’)(y’ + z) = w’ + x’ + yy’ + yz + z’y’ + z’z = w’ + x’ + 0 + yz + z’y’ + 0 = w’ + x’ + yz + y’z’

Principle of Duality Any theorem or identity in switching algebra remains true if  and + are swapped. The dual of a boolean function F is called FD It apply to all theorems that we worked with so far FD(X1,X2,…,Xn,+,.,’) = F(X1,X2,…,Xn,.,+,’) Parentheses has to be added to clarify precedence rules before the conversion

Principle of Duality Example: DeMorgan’s Laws – the second law is the dual of the first law (X+Y)’ = X’Y’  (X  Y)’ = X’ + Y’ Another Example: Covering Theorem X + X Y = X The dual is: X  X + Y = X X + Y = X WRONG!!! Why? Use parentheses to avoid problems X+(X.Y) then X.(X+Y)

Positive and Negative Logic Positive Logic: the higher voltage (+V) represents 1 and the lower voltage (0V) represents 0 Negative Logic: the higher voltage (+V) represents 0 and the lower voltage (0V) represents 1

Positive and Negative Logic (example) Gate e2 e3 e1 eo Electric Voltages Positive Logic Negative Logic The same physical circuit implements different logic functions. The function implemented depends on the logic used to interpret the inputs and outputs.

NAND: A Functionally Complete Logic Gate B C=(A·B)’ We can create all three gates (AND, OR, NOT) from NAND NAND as an Inverter A C=(A·A)’ = A’ A B (A·B)’ NAND as an AND C= ((A.B)’)‘= A.B A’ A C= (A’.B’)’ = A+B NAND as an OR B’ B

Is NOR Functionally Complete? Prove it yourself! A B C = (A+B)’

Exclusive OR, X-OR, or XOR X  Y = XY’ + X’Y X Y C If X=1 OR Y=1, but not both of them, then C=1 Commutative Law: X  Y = Y  X X  0 = X  1 = X  X = X  X’ = X X’ 1 Associative Law: (X  Y)  Z= X  ( Y  Z) = X  Y  Z Distributive Law: X(Y  Z) = XY  XZ

Exclusive-OR (cont.) Complement Law: (X  Y)’ = X  Y’ = X’  Y Algebraic Proof: (X  Y)’ = (XY’ + X’Y)’ = (XY’)’(X’Y)’ = (X’ + Y)(X + Y’) = X’X + X’Y’ + XY + YY’ = 0 + X’Y’ + XY + 0 = X’Y’ + XY = X’  Y = XY + X’Y’ = X  Y’

Equivalence Gate (X  Y) = XY + X’Y’ X Y C If X=Y then C=1, otherwise C=0 (X  Y) = (X  Y)’

Switch Networks and Switch Design Basic Ideal Switch: simplest structure in a computing system is a switch Path exists between INPUT and OUTPUT if Switch is CLOSED or ON Path does not exist between INPUT and OUTPUT if SWITCH is OPEN or OFF

Switches in Series Truth Table S1 S2 Path? AND Configuration

Switches in Parallel Truth Table S1 S2 Path? OR Configuration

CMOS Switches The idea is to use the series and parallel switch configurations to route signals in a desired fashion. Unfortunately, it is difficult to implement an ideal switch as given. Complementary Metal Oxide Semiconductor (CMOS) devices give us some interesting components. (INPUT) (OUTPUT) (INPUT) (OUTPUT)

CMOS Transfer Characteristics nMOS when CLOSED • Transmits logic level 0 well • Transmits logic level 1 poorly pMOS when CLOSED • Transmits logic level 1 well • Transmits logic level 0 poorly

CMOS Transmission Gate

CMOS Transmission Gate

High Impedance Z With switches, we can consider three states for an output: Logic-0 Logic-1 High Impedance Z Path exists for Logic-0 and Logic-1 when the switch is CLOSED. High impedance is a state where the switch is OPEN.

High Impedance Z Another way of thinking of switches is as follows: Path exists for Logic-0 and Logic-1 when the switch is CLOSED, meaning that the impedance/resistance is small enough to allow ample flow of current. High impedance is a state where the switch is OPEN, meaning that the impedance/resistance is very large allowing nearly no current flow.

Inverter (NOT) Network Truth Table Pull-Up Pull-Down Pull-Up A B A B A B 1 Z 1 Pull-Down 1 Z 1 1 Inverter (NOT) Gate B = A’ = A A B

NAND Network Pull-Up Pull-Down Truth Table A B C A B C A B C 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1 NAND (NOT AND) Gate A C C = (A.B)’ = (AB)’ = AB B

NOR Network Pull-Up Pull-Down Truth Table A B C A B C A B C 0 0 1 0 0 1 0 0 Z 0 0 1 0 1 Z 0 1 0 0 1 0 1 0 Z 1 0 0 1 0 0 1 1 Z 1 1 0 1 1 0 NOR (NOT OR) Gate A C C = (A+B)’ = (A+B)’ = A+B B

AND Network NAND Inverter Truth Table A B C 0 0 0 C 0 1 0 1 0 0 1 1 1 0 0 0 C 0 1 0 1 0 0 1 1 1 AND Gate A C C = A.B = AB B

OR Network NOR Inverter Truth Table A B C 0 0 0 0 1 1 C 1 0 1 1 1 1 0 0 0 0 1 1 C 1 0 1 1 1 1 OR Gate A C C = A+B B

XOR Network Truth Table A B C 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 XOR (Exclusive OR) Gate A C C = A  B = AB’ + A’B B

XNOR (Equivalence) Network Truth Table A B C 0 0 1 C 0 1 0 1 0 0 1 1 1 A C B XNOR or Equivalence Gate A C = A  B = AB + A’B’  C B