CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson & Hennessy, ©2005 Some slides and/or pictures in the following are adapted from: slides ©2008 UCB 14

Hardware Description Languages Basic idea: Language constructs and code describe circuits –text-based way to describe and exchange designs Originally introduced for circuit simulation –can simulate the operation of a circuit before we build it in silicon (easier to debug a model of the circuit rather than the real circuit in silicon) Now “logic synthesis” tools exist for automatic generation of lower- level logic circuit designs from high-level specifications HDL specification SimulationSynthesis

Verilog HDL One of two popular standard language (VHDL is the other) –C-like syntax –widely used in industry For purposes of describing our circuits, we will use only a simple subset of the language –will focus just on those language constructs used for “structural composition” – sometimes referred as “gate-level modeling” –these constructs allow us to instantiate primitive logic elements (logic gates) on our own circuit elements and connect them together with wires –very similar to what we would do if we were to wire together physical logic gates in a hardware lab

Verilog Introduction The module describes a component in the circuit Two ways to describe –Structural Verilog List of components and how they are connected One-to-one correspondence to the actual circuit The way we will describe our circuits –Behavioral Verilog Describe what a component does, not how it does it Useful before details of the actual circuit is worked out Useful for describing the test algorithm for another circuit

Verilog Introduction Build up a hierarchy of modules. Top-level module is your entire design (or the environment to test your design) Warning! –Even though we use language constructs to describe hardware that doesn’t mean that hardware design is equivalent to writing software –Describing circuits is not equivalent to programming –Therefore, to help keep you out of trouble, when describing circuits, in this class we will restrict our use of Verilog to structural constructs

Two-input Multiplexor Example (DONE IN CLASS)

Verilog big idea: Time in code One difference from a programming language is that time is part of the language –part of what we are trying to describe is when things occur, or how long things will take In both structural and behavioral Verilog, determine time with #n : event will take place in n time units –structural: not #2 (notX, X) says notX does not change until time advanced 2 ns –Default unit is nanoseconds; can change

2-input Mux with delay module mux2 (in0, in1, select, out); input in0, in1, select; output out; wire s0, w0, w1; not #1 (s0, select); and #1 (w0, s0, in0), (w1, select, in1); or #1 (out, w0, w1); endmodule

Testing in Verilog Code examples so far define hardware modules Need separate code to test the module (just like C/Java) Since hardware is hard to build, major emphasis on testing in HDL Testing modules called “test benches” in Verilog Could design special hardware blocks to test other blocks – awkward! Use behavioral Verilog to help

Testing the Multiplexor Create a test module for mux2 module testmux; reg a, b, s; wire f; reg expected; mux2 myMux(.select(s),.in0(a),.in1(b),.out(f)); /* add testing code */ endmodule Outline: declare variable to use for connection from testbench, instantiate module, specify stimulus, compare output to expected, print results

Testing the Multiplexor Now we write the code to try different inputs by assigning to connections... begin #0 s=0; a=0; b=1; expected=0; #10 a=1; b=0; expected=1; #10 s=1; a=0; b=1; expected=1; #10 $stop end

Testing the Multiplexor Use $monitor to watch some signals and see every time they are updated... initial $monitor(“select=%b in0=%b in1=%b out=%b, expected out=%b time=%d”, s,a,b,f,expected, $time); endmodule $time is system function which gives current (simulated) time

Testing the Multiplexor module testmux; reg a, b, s; reg expected; mux2 myMux(.select(s),.in0(a),.in1(b),.out(f)); initial begin #0 s=0; a=0; b=1; expected=0; #10 a=1; b=0; expected=1; #10 s=1; a=0; b=1; expected=1; #10 $stop end initial $monitor(“select=%b in0=%b in1=%b out=%b,expected out=%b time=%d”,s,a,b,f,expected,$time); endmodule