Lecture 5 A Closer Look at Instruction Set Architectures Lecture Duration: 2 Hours

AOU – Fall Lecture Overview  Introduction  Instruction formats Introduction Design Decisions for Instruction Sets Little VS Big Endian Internal Storage in the CPU Number of operands and Instruction Length Expanding Opcodes  Instruction types  Addressing

AOU – Fall Introduction (1/1) Introduction  This chapter builds upon the ideas in Chapter 4.  We look at different instruction formats, operand types, and memory access methods.  We will see the interrelation between machine organization and instruction formats.  This leads to a deeper understanding of computer architecture in general.

AOU – Fall Instruction formats – Introduction (1/2) Instruction formats  In Chapter 4 we saw that MARIE have an instruction length of 16 bits and could have, at most, 1 operand  In another architecture, those could be different  So, computer architectures generally differs by their Instructions Set format.  An Instruction Set can be described by its features.

AOU – Fall Instruction formats – Introduction (2/2) Instruction formats  The Instruction set’s features are: Number of bits per instruction: 12, 32 and 64 are the most common Type of the CPU elementary memory: Stack-based or register-based (this will affect the instruction format) Number of operands per instruction: Zero, one, two, and three being the most common. Operand location: register-to-register, register to- memory or memory-to-memory instructions. Types of operations: not only types of operations but also which instructions can access memory and which cannot. Type and size of operands: operands can be addresses, numbers, or even characters.

AOU – Fall Design Decisions for Instruction Sets (1/4) Instruction formats  During the design phase of a computer architecture, the Instruction set must be optimized. The instruction set must match the architecture. It must also maximize the efficiency of the computer architecture.  The first thing to define during the design phase is the instruction set format. To understand how this choice is made, we should know first, how we measure the efficiency of an ISA.

AOU – Fall Design Decisions for Instruction Sets (2/4) Instruction formats  Instruction set architectures are measured according to: Main memory space occupied by a program. Instruction complexity: amount of decoding necessary to execute an instruction (number of clock cycles per instruction) Instruction length (in bits). Total number of instructions in the instruction set.

AOU – Fall Design Decisions for Instruction Sets (3/4) Instruction formats  So, things to consider when designing an instruction set include: Instruction length -Short Vs long instructions: → shorter instructions take up less space in memory → shorter instructions can be fetched quickly → shorter instructions limit the number of instructions  → shorter instructions limit the number of operands  -Variable length VS fixed length instructions: → Fixed length instructions are easier to decode → but Fixed length instructions waste space 

AOU – Fall Design Decisions for Instruction Sets (4/4) Instruction formats  Things to consider when designing an instruction set include: Number of operands -Fixed number : Zero, one, two, and three being the most common -Variable number of operands (even if we have a fixed length instructions): Expanding opcode (to be explained in this lecture!) Addressable registers -How many? (number of registers) -How are they stored in the CPU? Memory organization -Word addressable or byte addressable? -A byte addressable architecture uses little or big endian concept? (to be explained in this lecture!) Addressing modes -Direct, indirect, immediate, indexed, etc. (to be explained in this lecture!)

AOU – Fall Lecture Overview  Introduction  Instruction formats Introduction Design Decisions for Instruction Sets Little VS Big Endian Internal Storage in the CPU Number of operands and Instruction Length Expanding Opcodes  Instruction types  Addressing

AOU – Fall Little VS Big Endian (1/5) Instruction formats  If we have a 32 bit data word, how we store this word in a byte addressable memory? The Least significant byte first? Of the most significant byte first?  Byte ordering, or endianness, is a major architectural consideration  We distinguish two concepts for byte ordering: Little Endian: A byte with a lower significance is stored in a lower address Big Endian: A byte with a higher significance is stored in a lower address

AOU – Fall Little VS Big Endian (2/5) Instruction formats  Example 1: consider an integer requiring 4 bytes: On a little endian machine, this is arranged in memory as follows: Base Address + 0 → Byte0 Base Address + 1 → Byte1 Base Address + 2 → Byte2 Base Address + 3 → Byte3 Byte 3Byte 2Byte 1Byte 0

AOU – Fall Little VS Big Endian (3/5) Instruction formats  Example 2: consider an integer requiring 4 bytes: On a big endian machine, this long integer would then be stored as: Base Address + 0 → Byte3 Base Address + 1 → Byte2 Base Address + 2 → Byte1 Base Address + 3 → Byte0 Byte 3Byte 2Byte 1Byte 0

AOU – Fall Little VS Big Endian (4/5) Instruction formats  Example 3: On a byte-addressable machine, the 32-bit hex value is stored at address 0. How is this value stored in memory if the machine uses a Big Endian concept? A little Endian concept? Answer:

AOU – Fall Little VS Big Endian (5/5) Instruction formats  Advantages of Big Endian: Is more natural: The most significant byte comes first (lower address). The sign of the number can be determined by looking at the byte at address offset 0. Strings and integers are stored in the same order.  Advantages of Little Endian: Makes it easier to place values on non-word boundaries. High-precision arithmetic is fast and easy.

AOU – Fall Lecture Overview  Introduction  Instruction formats Introduction Design Decisions for Instruction Sets Little VS Big Endian Internal Storage in the CPU Number of operands and Instruction Length Expanding Opcodes  Instruction types  Addressing

AOU – Fall Internal Storage in the CPU: Stacks VS Registers (1/5) Instruction formats  Another consideration for architecture design concerns how the CPU will store data.  We have three choices: A stack architecture. An accumulator architecture. A general purpose register architecture.  Designers choosing an ISA must decide which will work best in a particular environment and examine the tradeoffs carefully

AOU – Fall Internal Storage in the CPU: Stacks VS Registers (2/5) Instruction formats  Stack Architecture A stack is used to execute instructions Instructions and operands are implicitly taken from the stack Advantages -Good code density -Simple model for evaluation of expressions Disadvantages -A stack cannot be accessed randomly -Difficult to generate efficient code

AOU – Fall Internal Storage in the CPU: Stacks VS Registers (3/5) Instruction formats  Accumulator architectures One operand of a binary operation is implicitly in the accumulator -Example: MARIE Advantages -Reduce the internal complexity of the machine -Allow very short instructions Disadvantages -Memory traffic is very high (since one operand is in memory)

AOU – Fall Internal Storage in the CPU: Stacks VS Registers (4/5) Instruction formats  General purpose register architectures (GPR) General purpose registers can be used instead of memory Advantages -Registers are faster than memory -Easy for compilers to deal with -Can be used very effectively and efficiently Disadvantages -Long Instructions, long fetch and decode times

AOU – Fall Internal Storage in the CPU: Stacks VS Registers (5/5) Instruction formats  General purpose register architectures (GPR) GPR are the most widely accepted models for machine architectures today There are three types of GPR -Memory-memory architectures: may have two or three operands in memory, allowing an instruction to perform an operation without requiring any operand to be in a register. -Register-memory architectures: require a mix, where at least one operand is in a register and one is in memory. -Load-store architectures: require data to be moved into registers before any operations on that data are performed.

AOU – Fall Lecture Overview  Introduction  Instruction formats Introduction Design Decisions for Instruction Sets Little VS Big Endian Internal Storage in the CPU Number of operands and Instruction Length Expanding Opcodes  Instruction types  Addressing

AOU – Fall Number of operands and Instruction Length (1/6) Instruction formats  On current architectures, instructions can be formatted in two ways: Fixed length: Wastes space but is relatively fast. Variable length: Complex to decode but saves storage space.  In this course, we will be interested in Fixed length instructions.  In such instructions, we define the maximum number of operands (this number has a direct impact on the length of the instruction itself)

AOU – Fall Number of operands and Instruction Length (2/6) Instruction formats  Example: MARIE uses a fixed-length instruction with a 4-bit opcode and 12-bit operand. In MARIE the maximum number of operands is one. Though, some instructions for MARIE have no operand (for instance: halt).

AOU – Fall Number of operands and Instruction Length (3/6) Instruction formats  The most common instruction formats include zero, one, two, or three operands: Zero operand -OPCODE only One operand (usually a memory address) -OPCODE + 1 Address Two operands (usually registers, or one register and one memory address) -OPCODE + 2 Addresses Three operands (usually registers, or combinations of registers and memory) -OPCODE + 3 Addresses

AOU – Fall Number of operands and Instruction Length (4/6) Instruction formats  Machine instructions that have no operands must use a stack  In architectures based on stacks, most instructions consist of opcodes only; however, there are special instructions that have just one operand: Push X places the data value found at memory location X onto the stack Pop X removes the top element in the stack and stores it at location X

AOU – Fall Number of operands and Instruction Length (5/6) Instruction formats  Example: Suppose we wish to evaluate the following expression: Z = (X x Y) + (W x U)  The assembly code would be: For a Three operand ISAFor a Two operand ISAFor a one operand ISA (such as MARIE!) Mult R1, X, Y Mult R2, W, U Add Z, R2, R1 Load R1, X Mult R1, Y Load R2, W Mult R2, U Add R1, R2 Store Z, R1 Load X Mult Y Store Temp Load W Mult U Add Temp Store Z

AOU – Fall Number of operands and Instruction Length (6/6) Instruction formats  Example: Suppose we wish to evaluate the following expression: Z = (X x Y) + (W x U) In a stack architecture the assembly code would be : For a zero operand ISA Push X Push Y Mult Push W Push U Mult Add Store Z X Y X X x Y Push Y Mult Push W; Push U U W W x U Mult W x U X x Y Add X x Y + W x U Stack

AOU – Fall Lecture Overview  Introduction  Instruction formats Introduction Design Decisions for Instruction Sets Little VS Big Endian Internal Storage in the CPU Number of operands and Instruction Length Expanding Opcodes  Instruction types  Addressing

AOU – Fall Expanding Opcodes (1/9) Instruction formats  We have seen how instruction length is affected by the number of operands supported by the ISA.  In any instruction set, not all instructions require the same number of operands.  Operations that require no operands, such as HALT, necessarily waste some space when fixed- length instructions are used.  One way to recover some of this space is to use expanding opcodes.

AOU – Fall Expanding Opcodes (2/9) Instruction formats  The idea of expanding opcodes is to make some opcodes short, but have a means to provide longer ones when needed.  When the opcode is short, a lot of bits are left to hold operands So, we could have two or three operands per instruction  If an instruction has no operands (such as Halt), all the bits can be used for the opcode Many unique instructions are hence available  In between, there are longer opcodes with fewer operands as well as shorter opcodes with more operands.

AOU – Fall Expanding Opcodes (3/9) Instruction formats  Example 1: Consider a machine with 16-bit instructions and 16 registers. The instruction format can have several structures: -Opcode + Memory address (such as MARIE): → If we have 4KB byte addressable memory we need 12 bits to specify an address location → The remaining 4 bits are used for the opcode: 16 instruction are hence available -Opcode + Registers Addresses → we need 4 bits to select one of the 16 available registers → Suppose we have 4 bits opcode, we could encode 16 different instructions with three operands each (3 x 4 bits = 12 bits).

AOU – Fall Expanding Opcodes (4/9) Instruction formats  Example 2: Consider a machine with 16-bit instructions and 16 registers. And we wish to encode the following instructions: -15 instructions with 3 addresses -14 instructions with 2 addresses -31 instructions with 1 address -16 instructions with 0 addresses Can we encode this instruction set in 16 bits? Answer: Yes if we use expanding opcodes

AOU – Fall Expanding Opcodes (5/9) Instruction formats  One possible encoding is as follows: Is there something missing from this instruction set?

AOU – Fall Expanding Opcodes (6/9) Instruction formats  How do we know if the instruction set we want is possible when using expanding opcodes? We must determine if we have enough bits to create the desired number of bits patterns

AOU – Fall Expanding Opcodes (7/9) Instruction formats  Going back to Example 2 (Slide 33): The first 15 instructions account for: 15x2 4 x2 4 x2 4 = 15 x 2 12 = bit patterns The next 14 instructions account for: 14 x 2 4 x 2 4 = 15 x 2 8 = 3584 bit patterns The next 31 instructions account for: 31 x 2 4 = 496 bit patterns The last 16 instructions account for 16 bit patterns In total we need = different bit patterns Having a total of 16 bits we can create 216 = bit patterns We have an exact match with no wasted patterns. So our instruction set is possible.

AOU – Fall Expanding Opcodes (8/9) Instruction formats  Example 3: Is it possible to design an expanding opcode to allow the following to be encoded with a 12-bit instruction? Assume a register operand requires 3 bits. 4 instructions with 3 registers 255 instructions with 1 register 16 instructions with 0 register

AOU – Fall Expanding Opcodes (9/9) Instruction formats  Solution: The first 4 instructions account for: -4x2 3 x2 3 x2 3 = 4 x 2 9 = 2048 bit patterns The next 255 instructions account for: -255 x 2 3 = 2040 bit patterns The last 16 instructions account for 16 bit patterns In total we need = 4104 bit patterns With 12 bit instruction we can only have 2 12 = 4096 bit patterns Required bit patterns (4104) is more than what we have (4096), so this instruction set is not possible with only 12 bits.

AOU – Fall Lecture Overview  Introduction  Instruction formats  Instruction types  Addressing

AOU – Fall Instruction types (1/4) Instruction types  Instructions fall into several broad categories: Data movement instructions -The most frequently used instructions -Data is moved from memory into registers, from registers to registers, and from registers to memory -Examples: Load, Store, Move, Push, Pop, etc. Arithmetic instructions -Include those instructions that use integers and floating point numbers. -As with the data movement instructions, there are sometimes different instructions for providing various combinations of register and memory accesses in different addressing modes. -Examples: Add, Subtract, Multiply, Increment, Decrement, etc.

AOU – Fall Instruction types (2/4) Instruction types  Instructions fall into several broad categories: Boolean Instructions -Perform Boolean expressions. -Commonly used to control I/O devices. -Examples: Not, Or, Xor, Test, compare, etc. Bit manipulation instructions -Used for setting and resetting individual bits (or sometimes groups of bits) within a given data word. -Examples: Shift left, shift right, rotate left, rotate right

AOU – Fall Instruction types (3/4) Instruction types  Instructions fall into several broad categories: I/O instructions -Used to communicate with input/output devices -Examples: Input, Output. Control transfer Instructions -Include branches, skips and procedure calls. -Examples: For MARIE we have Jump, skipcond and JnS. Special purpose Instructions -Include those used for string processing, high-level language support, protection, flag control, and cache management.

AOU – Fall Instruction types (4/4) Instruction types  When designing an instruction set for a given architecture, we must respect the following: Create a complete instruction set. Be carful not to add redundant instructions We should respect instructions orthogonality -Each instruction should perform a unique function without duplicating any other instruction

AOU – Fall Lecture Overview  Introduction  Instruction formats  Instruction types  Addressing Introduction Addressing Modes

AOU – Fall Addressing - Introduction Addressing  Addressing modes specify where an operand is located.  They can specify a constant, a register, or a memory location.  The actual location of an operand is its effective address.  Certain addressing modes allow us to determine the address of an operand dynamically.

AOU – Fall Addressing Modes (1/10) Addressing  Immediate addressing The data is part of the instruction. Example: Load 008 -The numeric value 8 is loaded into the AC  Direct addressing The address of the data is given in the instruction. Example: Load 008 -The data value found at memory address 008 is loaded into the AC  Register addressing The data is located in a register. Example: Load R1. -The contents of R1 register is used as the operand.

AOU – Fall Addressing Modes (2/10) Addressing  Indirect addressing Gives the address of the address of the data in the instruction. Example Load 008 -The data value found at memory address 008 is actually the effective address of the desired operand. → Suppose we find the value 2A0 stored in location 008. → 2A0 is the “real” address of he value we want. → The value found at location 2A0 is then loaded into the AC

AOU – Fall Addressing Modes (3/10) Addressing  Register indirect addressing Uses a register to store the effective address of the data. Works exactly the same way as indirect addressing mode, except it uses a register instead of a memory address to point to the data. Example: Load R1 -The effective address of the desired operand is found in R1.

AOU – Fall Addressing Modes (4/10) Addressing  Indexed addressing uses a register (implicitly or explicitly) as an offset, which is added to the address in the operand to determine the effective address of the data. Example: Load X, where the index register holds the value 1. -The effective address of the operand in actually X + 1

AOU – Fall Addressing Modes (5/10) Addressing  Based addressing Similar to indexed addressing except that a base register is used instead of an index register. An index register holds an offset relative to the address given in the instruction, but a base register holds a base address where the address field represents a displacement from this base. Example: Load 3, where the base register holds the address value X. -The effective address of the operand is actually X +3  Stack addressing The operand is assumed to be on top of the stack.

AOU – Fall Addressing Modes (7/10) Addressing  Example: For the instruction shown, what value is loaded into the accumulator for each addressing mode? 800

AOU – Fall Addressing Modes (8/10) Addressing  Example: For the instruction shown, what value is loaded into the accumulator for each addressing mode?

AOU – Fall Addressing Modes (9/10) Addressing  Example: For the instruction shown, what value is loaded into the accumulator for each addressing mode?

AOU – Fall Addressing Modes (10/10) Addressing  Example: For the instruction shown, what value is loaded into the accumulator for each addressing mode? = 1600

End of lecture 5 Try to solve all exercises related to lecture 5