Baseband Implementation of an OFDM System for 60GHz Radios: From Concept to Silicon Jing Zhang University of Toronto

System Overview FEC Encoder Constellation Mapping IFFT GI Insertion & Time Domain Windowing FEC Decoder Constellation Demapping Freq. Domain Correction GI Removal Freq. Domain Processing Channel Estimation Synchronization FFT Modulation Core DAC & RF RF & ADC Channel Demodulation Core Data rate up to 1.6 Gbps (Possible application: Gigabit Wireless Ethernet) BPSK/QPSK/16QAM 1K point FFT/IFFT, 512 MHz sampling frequency

Design Challenges Meeting performance specification Multi-disciplinary design [communication theory to silicon] Design methodology challenge: Correctness & Efficiency in design representation, synthesis and verification. Tools and Flow needed. Behavior Model Architecture Model RTL Model Silicon Initial Concept Mature EDA tools available System (Behavior/Algorithm) Level Design Architecture Level Design Register Transfer Level Level Design Back-end Flow (Physical Level Design) Design synthesis Design Verification: verify against upper level model

System Level Design Performance Target (Data rate, BER…) OFDM Calculator Design Constraints (BW, Channel…) Design Parameters (FFT Size GI Length…) Meet Spec.? Rapid Design ExplorationDetailed Simulation Architecture Design N Y Floating Point Matlab Model Simulation

Architecture Level Design Statistical Analysis Fixed Point Matlab Model Simulation Word Length Meet Spec.? N Y Word-length Fine-tune Macro Architecture Design Micro Architecture Design Architecture Specification Finite-Word-Length effect evaluation is critical and time consuming Macro architecture design Functional block identification and interface definition Global control and data flow arrangement Micro architecture design Pipelining and Parallel processing unit arrangement Detailed data-path and local control design Finite-Word-Length Effect EvaluationArchitecture Mapping

RTL Level Design & Physical Design RTL Coding Fixed Point Matlab Model Reference Model Simulation RTL Simulation Logic Synthesis Architecture Specification Fixed point Matlab model serves as the reference model for RTL model verification Stimulus and response files used in the testbench of RTL simulation Logic synthesis and P&R: scripts widely used to speed up iteration Design result: Die size: 4.05 mm by 4.85 mm, in TSMC 0.18μm 6LM CMOS process I/O Signals: 76 Performance: 4 parallel pipelines running at 135 MHz Stimulus & Response files Place & Route GDSII