APSR Matthew Bailes Swinburne University Of Technology.

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Presentation transcript:

APSR Matthew Bailes Swinburne University Of Technology

Baseband Pulsar Timing History  Caltech Berkeley Processor  MHz 2xDLT 7000  Princeton Mk IV  MHz 2xDLT 7000  S2TCI (~1997)  York University/Melbourne Uni/Swinburne  16 MHz 8xVHS  CPSR1 (~1999)  Caltech/Swinburne  4xDLT 7000

Baseband History  COBRA  Coherent Baseband Recorder 2001?  150+ Processors  CPSR2 (2002)  2x64 MHz x 2bits x 2 pols  30 Xeon dual processors  Arecibo Signal Processor (ASP) 03/04?  64 MHz with polyphase filters and 4 bits

Selected Achievements  Princeton Mk IV  MSP timing, ~200 ns timing on  PUMA2??  CPSR1  130 ns timing on PSR J  CPSR2  Polarimetry of 27 MSPs  Giant Pulses discovered in MSPs  Precision timing on 7 MSPs (< 1 us)  0437, 0613, 1600, 1713, 1744, 1909, 1937  Several others near ~1 us

Giant Pulses Giant Pulse 2 microseconds wide!

Timing 75 nanosecs

Stability

Profile Precision Must be done with Coherent dedispersion

New DFB Limitations  2048 channels/ 512 MHz  L-band  Terzan 5  190 us Smearing!  Still need coherent dedispersion

Current Generation IF Samplers + FPGA Bits Polyphas e bits CPU 1 Gb ethernet Gb SwitchCPU

Next Generation  “APSR”  ATNF/Parkes/Swinburne/Recorder  1 GigaByte/sec recorder/processor  Much higher timing precision  Nanosecond pulse sensitivity  Lunar Experiments  Giant pulses  Pulsar searches  Polarimetry  Spectroscopy  VLBI correlator?

APSR IF Samplers + FPGA Bits Polyphas e bits CPUs x16 Gb ethernet x16 Gb Switch 144 ports min CPU x128 1 GHz x 2

Specs  Limited to 64 MB/s per host  Current Gb limit  16 Primaries  64 MB/s  2 bits x 64 MHz x 2 pols 3 GHz  4 bits x 32 MHz x 2 pols L-band  8 bits x 16 MHz x 2 pols Bright Pulsars

Primary Machines  3 GB RAM  Gb ethernet x 2  500 GB SATA disks  16 of them

Secondaries  Low-voltage next-gen Pentium  2 GB RAM (min)  2 x 250 GB SATA drives  Probably rack-mounted  Gb ethernet

Switch  144 ports  Gb ethernet  10 Gb uplink  Probably CISCO

Costings  Primaries: 48 K  Secondaries: 128 K  Switch: 12K  Cabling: 8K  Racks: 15K  Total: 211K

Required Modes:  Mode 1  Raw data x 16  2 bits x 64 Msamples/sec x 2 pols x 16 (agg 1 GHz)  4 bits x 32 Msamples/sec x 2 pols x 16 (agg 512 MHz)  8 bits x 16 Msamples/sec x 2 pols x 16 (agg 256 MHz)  Mode 2  Polyphase FB  2 bits x 64 MHz x 2 pols x 16 (agg 1024 MHz)  4 bits x 32 MHz x 2 pols x 16 (agg 512 MHz)  8 bits x 16 MHz x 2 pols x 16 (agg 256 MHz)

Required Modes:  Mode 3  Polyphase FB - single host  2048 chans x 2/4/8 bits x Npol x 32 us sampling  Up to 64 MB/s  Mode 4  Polyphase FB - multi-host  16 x PPFB x nbits x nchans x Npol x Nus samples  Mode 4  As for 3, but incoherently dedispersed into N channels  Mode 6  As for 4, but coherently dedispersed  Mode 7  As for 3, but folded for N PSRs simultaneously  Mode 8  As for 6, but folded for N PSRs simultaneously

Other Wishes: New digital FB for next MB survey 13 DFBs with 300 MHz BW, 2048 channels, 64 us sampling

APSR 16 Primaries Switch 128 CPUs 10 Gb To Grangenet Ghz DFB 16?xDFB IFs 13xIFs GHz Apple XRAIDs 16? lines ?

Aggregate Power  CPUs:  128 x 4GHz x 4flops/cycle = 2 Teraflops  Disk:  64 Terabytes (17 hours recording)  Pulsar surveys in real time

Issues:  Heat dissipation  144 x 150 W = 20 KW!!  Multiplexing IO to CPUs  How can I take 1 GB/sec and spread it 16 ways without losing bits??

Upon Completion:  Throw out:  CPSR2  WBC  DFB1  MB correlators  Analogue Filters  VLBI recorders