AFE Meeting June 5, 2001 SIFT UPGRADE Marvin Johnson

AFE Meeting June 5, 2001 Background  SVX 2 readout choice u wanted common readout electronics u Charge signal was roughly comparable to silicon u SVX 3 development precluded new SVX chip u Chip was “free”  SIFT development u UC Davis project u Subcontracted to commercial firm u design is not robust s component variation s external noise on threshold s parasitic C on SIFT output  SVX 2 has problems in MCM package

AFE Meeting June 5, 2001 What’s Changed?  Biggest change is in FPGAs u Emulate SVX II for readout u Buffer 64 or 128 data points u Zero suppress the data on the fly.  Fast and inexpensive FLASH ADC converters  Existence of.25 micron designs at FNAL that can be dropped in to new chip designs

AFE Meeting June 5, options  Direct SIFT replacement  SIFT replacement but include pipeline (18 channel)  Replace entire MCM without using the SVX II chip.

AFE Meeting June 5, 2001 Direct Replace  Requires replacement of SIFT in existing MCM’s  Potentially the lowest cost u may have yield problems  Keeps problems with SVX u Input is always open u differential non linearity  Requires a lot of FNAL manpower  New process that has a great deal of unknown risks

AFE Meeting June 5, 2001 SIFT+Pipeline  Only change is to add the pipeline delay to the SIFT u Allows the SVX to be cleared before charge transfer u Eliminates SVX pickup

AFE Meeting June 5, 2001 NEW MCM  Mux analog out to a flash ADC u 10 bit Flash ADC, 2 channels/chip u 3 micro s total conversion time s allows 94 ns/conversion  Chip control from an FPGA  Make daughter board same footprint as MCM  Power consumption appears similar to current MCM  Solves both CFT and preshower in one board

AFE Meeting June 5, 2001 Details  Pipe line is in 0.25 micron. u convert preamp to 0.25 u should part be made rad hard?  Use gate array to zero suppress and put data into SVX format u how to pack 10 bits into format.  Do we need 2 disc. levels? u If yes, how does it get to virtual SVX.  Do we implement digital controls? u how is down loading done?  How is power handled?

AFE Meeting June 5, 2001 schedule and cost  TSMC submission in November u $175K for 10 wafers (6 guaranteed) u Share submission with BTEV pixel u get enough chips for project (if OK) s ~1000 chips/wafer u Packaging cost is $5/chip $15K u chip testing done at FNAL ~$30K  dual 12 bit ADC and FPGA for $30  Daughter board+stuffing for $50. u pair of adapter boards cost $75.  Total for 2000 is $160K u Is 2000 enough?  Need 50% contingency at this stage  $307K total without TSMC cost u incremental cost over SIFT only is ~$200K assuming labor at FNAL is free.  Done 1 year after submission u need to cycle all AFE boards

AFE Meeting June 5, 2001 Which Option?  FADC gets rid of DNL and readout problems.  Also reduces risk for changing the SIFT parts on MCM’s  FADC gives clean solution to CFT and Preshower  But, it costs more money.  Both solutions probably take the same time u SIFT replacement is more of an unknown u Need to try SIFT repair on 50 parts ASAP.  Chip designer needs to know what to do by the end of May