ABCN Pad ring V8.0 30/04/13F. Anghinolfi/K. Swientek1 Final ABC130 pads distribution

y x um um 4 off fiducials added Fiducials are 95µm x 95µm (Ball bond pad) mm x 7.9mm (x,y) ABC130 – Pad ring and Fiducials

ABC130 “BOTTOM SIDE” 30/04/13 F. Anghinolfi/K. Swientek PIO_REC PIO_REC160 SIOGND BC_padN CLK_PadN COM_LZERO_PadN LONERTHREE_padN 200 PIO_INP_RAW_PULLD OWN DGNFETProt padDisable_RegA padDisable_RegD padShuntCtrl SIOGND 250 SIOGND 250 SIOGND To FE To BE Chip edge 3150 um um BC_padP CLK_PadP COM_LZERO_PadP LONERTHREE_padP x40 um MA GNDD

ABC130 “RIGHT SIDE” (but represented horizontal to match the paper or.) 30/04/13 F. Anghinolfi/K. Swientek Follow up on next slide --  PIO_TRCVR PIO_INP padID (5) XoffLB DataLB 111 PIO_INP_PD 111 SIODVSS PIO_REC SIOGND 111 FastCLK_PadP padTerm To “Bottom” side Chip edge um Abut left pad of next slide = 391 um XoffL DataL FastCLK_PadN DVSS GNDD

ABC130 “RIGHT SIDE” (but represented horizontal to match the paper or.) 30/04/13 F. Anghinolfi/K. Swientek Follow up on next slide --  Digital Power/Ground (6 pads) Left Group SIOGND SIOVDD SIODVDD SIOGND SIOVDD SIODVDD 7*111 = 777 um SIODVSS DVSSBR GNDD VDDD DVDD GNDD VDDDDVDD DVSS Special Unit Abut left pad of next slide 5 All Power rings cut (BFMOAT) Distance from last supply here, DVSS to DVSSA in the next slide is 162 um 111

ABC130 “RIGHT SIDE” (but represented horizontal to match the paper or.) 30/04/13 F. Anghinolfi/K. Swientek Follow up on next slide --  Analog Power/Ground (16 pads) SIOGND SIOVDD SIODVDD 17* = 2049 GNDIT GNDA VDDA AVDD SIODVSS DVSSA Abut left pad of next slide 6 All Power rings cut (BFMOAT) SIODVSS DVSSA GNDIT SIOGND SIOVDD SIODVDD GNDIT GNDA VDDA AVDD SIOGND SIOVDD SIODVDD GNDIT GNDA VDDA AVDD SIOGND SIOVDD SIODVDD GNDA VDDA AVDD

ABC130 “RIGHT SIDE” (but represented horizontal to match the paper or.) 30/04/13 F. Anghinolfi/K. Swientek SIOGND SIOVDD SIODVDD Digital Power/Ground (9 pads) Right group SIOGND SIOVDD SIODVDD SIOGND SIOVDD SIODVDD 8* = 1014 um GNDD VDDDDVDD GNDD VDDDDVDD GNDD VDDDDVDD PIO_DRV PIO_TRCVR SIOGND 111 SIODVSS 111 DataoutFC1_PadN DATR XOFFR Chip edge To “Top” side 1577 um =382 um DataoutFC1_PadP DATRB XOFFRB DataoutFC2_PadN DataoutFC2_PadP SIODVSS DVSS GNDD

ABC130 “TOP SIDE” 30/04/13 F. Anghinolfi/K. Swientek SIOGND SIOVDD SIOGND PIO_INP_PD SIODVDD SIOGND GNDDVDDDGNDD abcup_pad VDDDGNDD Chip edge PIO_INP RSTB_pad PIO_INP_PD SIOBPU08_B_o utput PIO_INP_PD SIOBPU08_B_o utput PIO_ANA ScanEnableScan_in_CLKScan_in_BC Scan_out_CLKScan_out_BC SIOGND SIOVDD VDDD GNDD TESTCOM SIOGND GNDD SIOGND GNDD SIOGND GNDD Analogue Pads Attached to the Analogue FE block Power rails break x40 um MA ANA AMUXOUT TESTRES

6.8mm x 7.9mm (x,y) ABC130 – Placement on reticle <=21 <= (arbitrary) TDCpix ABC130 TDCpix_demo ABC ABC130 per reticle, 60 “good” reticles per wafer

6.8mm x 7.9mm (x,y) ABC130 – Pads list

Ashley’s Old 4 slides 30/04/13F. Anghinolfi/K. Swientek11 rather old

y x 6mm x 7.9mm (x,y) 200µm 250µm 200µm 250µm LVDS Rx placed on 200µm pitch Gnd pad, placed 250µm from LVDS pads (between centres) 450µm 250µm 3650µm BC RLCK L0_COM R3_L1 FE_GND GND Pad 700µm Pads placed on 125µm pitch A B C A: REG_A B: REG_D C: ShuntCtrl ABC130 Bottom Edge – Left Side Unless indicated ALL bond pads are 95µm x 190µm VSS (spare) pad omitted - but assume this GND serves the function?

y x 200µm 300µm 125µm 200µm 125µm 200µm 150µm 125µm XoffL DataL FC_CLK TERM Chip IDx Remaining Pad assignment as prescribed by Francis 125µm Pads step and repeat at 125µm pitch Fiducial 3 6mm x 7.9mm (x,y) ABC130 Bottom Edge – Bottom left corner

y x 200µm 125µm 200µm 125µm 200µm FC1 FC2 DataR XoffR G Remaining PAD assignment as prescribed by Francis P G P 275µm 125µm 200µm 150µm 125µm Pads step and repeat at 125µm pitch Fiducial 2 6mm x 7.9mm (x,y) ABC130 Bottom Edge – Top right corner

y x 7660µm 3875µm 120µm 4 off fiducials added Fiducials are 95µm x 95µm (Ball bond pad) mm x 7.9mm (x,y) ABC130 – Fiducial Detail