AHDL (Chapters 6 & 7). Using TTL Library Functions with HDL MSI chips such as adders and ALU ICs are the building blocks of digital systems. How to use.

Slides:



Advertisements
Similar presentations
Chapter 13 Shift Registers
Advertisements

Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.
Register Transfer Level
1ASM Algorithmic State Machines (ASM) part 1. ASM2 Algorithmic State Machine (ASM) ‏ Our design methodologies do not scale well to real-world problems.
Registers and Counters
Give qualifications of instructors: DAP
Chapter 9 Computer Design Basics. 9-2 Datapaths Reminding A digital system (or a simple computer) contains datapath unit and control unit. Datapath: A.
Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi
EEE515J1_L3-1/55 EEE515J1 ASICs and DIGITAL DESIGN Ian McCrumRoom 5D03B Tel: voice mail on 6 th ring.
Flip-Flops and Related Devices Wen-Hung Liao, Ph.D.
Chapter 10 Flip-Flops and Registers Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
Arithmetic Operations and Circuits
Flip-Flops and Related Devices Wen-Hung Liao, Ph.D. 4/10/2002.
Homework Reading Machine Projects Labs Tokheim Chapter 9.1 – 9.6
1 COMP541 Sequencing and Control Montek Singh Mar 29, 2007.
Flip-Flops and Related Devices
M.S.P.V.L. Polytechnic College, Pavoorchatram
Chapter 7 Arithmetic Operations and Circuits Hexadecimal Arithmetic 4 binary bits represent a single hexadecimal digit Addition –Add the digits.
Arithmetic Operations and Circuits
Chapter 1_4 Part II Counters
Combinational Logic in Verilog
Introduction to Digital Logic Design Appendix A of CO&A Dr. Farag
Chapter 6 – Digital Arithmetic: Operations & Circuits
ECE 2372 Modern Digital System Design
Introduction to Chapter 6  Digital circuits are frequently used for arithmetic operations  Fundamental arithmetic operations on binary numbers and digital.
Chapter 7 – Counters and Registers
Figure 5.1. Conversion from decimal to binary.. Table 5.1. Numbers in different systems.
ENG241 Digital Design Week #6 Sequential Circuits (Part A)
5-21 Schmitt-Trigger Devices
Flip-Flops and Registers
Introduction to Chapter 7
Sequential Design Basics. Lecture 2 topics  A review of devices that hold state A review of Latches A review of Flip-Flops 8/22/2012 – ECE 3561 Lect.
Introduction to Chapter 5  Logic circuits studied so far have outputs that respond immediately to inputs at some instant in time.  We now introduce the.
REGISTER TRANSFER & MICROOPERATIONS By Sohaib. Digital System Overview  Each module is built from digital components  Registers  Decoders  Arithmetic.
Chapter 0 deSiGn conCepTs EKT 221 / 4 DIGITAL ELECTRONICS II.
Synchronous Counters Synchronous digital counters have a common clock which results in all the flip-flops being triggered simultaneously. Consequently,
2017/4/24 1.
Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics VHDL register-transfer modeling: –basics using traffic light controller; –synthesis.
Discussed in class and on Fridays n FSMs (only synchronous, with asynchronous reset) –Moore –Mealy –Rabin-Scott n Generalized register: –With D FFs, –With.
ANALYSIS OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.
9/28/089/26/2008ECE Lecture1 Lecture 3 – Common Elements 9/26/20081ECE Lecture.
EKT 221 : Chapter 4 Computer Design Basics
Sequential logic circuits
CHAPTER 6 Sequential Circuits’ Analysis CHAPTER 6 Sequential Circuits’ Analysis Sichuan University Software College.
Verilog A Hardware Description Language (HDL ) is a machine readable and human readable language for describing hardware. Verilog and VHDL are HDLs.
Logic Design / Processor and Control Units Tony Diep.
Introduction to ASIC flow and Verilog HDL
ENG241 Digital Design Week #7 Sequential Circuits (Part B)
Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-1 Panorama of VLSI Design Fabrication (Chem, physics) Technology (EE) Systems (CS) Matel.
Synthesis Synchronous Sequential Circuits synthesis procedure –Word description of problem /hardest; art, not science/ –Derive state diagram & state table.
EKT 221 : Digital 2 Computer Design Basics Date : Lecture : 2 hrs.
Cpe 252: Computer Organization1 Lo’ai Tawalbeh Lecture #3 Flip-Flops, Registers, Shift registers, Counters, Memory 3/3/2005.
REGISTER TRANSFER & MICROOPERATIONS By Sohaib. Digital System Overview  Each module is built from digital components  Registers  Decoders  Arithmetic.
Common Elements in Sequential Design. Lecture 3 topics  Registers and Register Transfer  Shift Registers  Counters Basic Counter Partial sequence counters.
CHAPTER 14 Digital Systems. Figure 14.1 RS flip-flop symbol and truth table Figure
Ch.5 Flip Flops and Related Devices
Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved.
Digital Logic & Design Dr. Waseem Ikram Lecture No. 25.
Combinational Logic Design
Flip-Flops and Related Devices
FIGURE 5.1 Block diagram of sequential circuit
Dr. Clincy Professor of CS
Dr. Clincy Professor of CS
CHAPTER 4 COUNTER.
Digital Logic Department of CNET Chapter-6
Digital Logic Department of CNET Chapter-6
Chapter5: Synchronous Sequential Logic – Part 4
Chapter5: Synchronous Sequential Logic – Part 3
Chap. 7 Counters and Registers
Presentation transcript:

AHDL (Chapters 6 & 7)

Using TTL Library Functions with HDL MSI chips such as adders and ALU ICs are the building blocks of digital systems. How to use these components in HDL?  macrofunction A macrofunction is a self-contained description of a logic circuit with all its inputs, outputs and operational characteristics defined. Good documentation on the macrofunction is critical.

Function Prototype Example: (p. 343) 4-bit ALU with 8 different operations. FUNCTION 74382(s[2..0], a[3..0],b[3..0],cin)) RETURNS (ovr, cn4, f[3..0])

AHDL Macrofunctions Comments/documentation first Then Function prototype Then constant and global definitions INCLUDE derivative is allowed. Includes files with extension:.inc

Graphic Description of an 8-bit ALU

AHDL definition of an 8-bit ALU

Logic Operation on Bit Arrays SUBDESIGN bitwise_and (d[3..0], g[3..0]: INPUT; xx[3..0]: OUTPUT;) BEGIN xx[]= d[] & g[]; END; -- Note: x is a reserved identifier in AHDL, use xx

HDL Adders Block Symbol

AHDL 4-bit Adder

N-bit Adder/Subtractor

Library of Parameterized Modules Megafunctions: include a library of parameterized modules (LPMs) Offers a generic solution for the various types of logic circuits that are useful in digital systems. Parameterized means that when you instantiate a function from the library, you are specify some parameters that define certain attributes for the circuit. Example: LPM_ADD_SUB megafunction has a parameter LPM_WIDTH.

AHDL LPM Adder/Subtractor

Basic Counters in HDL Counters are constructed with FFs. In Chapter 5, we describe the FFs using AHDL. Becomes too tedious if we have to use multiple FFs. Describe circuits with a higher-level of abstraction. Will consider synchronous counters only.

Synchronous Counter Design with D FF Easier than using J-K FFs. The NEXT state of the D FF is the same as its PRESENT D input values. Example: Table 7-7

State Transition Description Methods List the PRESENT state/NEXT state table.

AHDL MOD-5 Counter

Another Version of MOD-5 Counter

Behavioral Description The behavioral level of abstraction is a way to describe circuit by describing its behavior in terms very similar to the way you might describe its operation in English. Deals more with the cause-and-effect relationship than with the path of data flow or wiring details.

Behavioral Description of a Counter

AHDL Full-Featured Counter

LPM Counters

State Machines

AHDL Registers

Data Transfers on Shift Registers

AHDL Bidirectional Shift Register

AHDL 4-Bit Ring Counter

AHDL Nonretriggerable One- Shot

Simulation

Detecting Edges

AHDL Retriggerable, Edge- Triggered One-Shot