EE3A1 Computer Hardware and Digital Design Worked Examples 3 Test and testability (1)

Worked Examples (a) Explain testability enhancement.[5] (b) Form Boolean difference of the output with respect to each of the inputs. [8] (c) Produce a set of test vectors that can test the inputs a,b,c for single s-a-0 and s-a-1 faults.[3]

Worked Examples (d) Signature analyser initialized to the all-zero state, and fed with (MSB first ). i) What is the fault-free signature? ii) Show that if the fifth bit is in error, the final signature is different from the fault-free case. [4]

Solution: part (b)  Form Boolean difference of the output with respect to each of the inputs. (c) Circuit function is Likewise for b and c Boolean proposition: if a changes then f will also change This is true when setting a=1 and a=0 give rise to different value for f f0f1f0 XOR f

Solution: Sensitivity to a (b) Circuit function is Using identity X  Y=X.Y+X.Y

Solution: Sensitivity to b (b) Circuit function is Using identity X  Y=X.Y+X.Y

Solution: Sensitivity to c (b) Circuit function is Using identity X  Y=X.Y+X.Y

Solution: part (b) What does this mean?

Meaning of Boolean Difference Truth table for f K-Map for f

Meaning of Boolean Difference K-Map for f Where b is changing: is true if change in b causes change in f Where change in f results

Meaning of Boolean Difference Where b is changing: K-Map for f is true if a change in b causes a change in f Where change in f results

Questions  What is the value of  (i.e. under what condition will a change in A cause a change in C) (a) a+b (b) 1 (c) a (d) b (e) b

Solution: part (c) Test a, b and c for s-a-0, s-a-1

Solution: part (c) node a Test a s-a-0 Set a=1 Make f sensitive to a b=0 Test vector abc=100 or 101 Test a s-a-1 Set a=0 Make f sensitive to a b=0 Test vector abc=000 or 001

Solution: part (c) node b Test b s-a-0 Set b=1 Make f sensitive to b ac=11 or 00 Test vector abc=111 or 010 Test b s-a-1 Set b=0 Make f sensitive to b ac=11 or 00 Test vector abc=101 or 000

Solution: part (c) node c Test c s-a-0 Set c=1 Make f sensitive to c b=1 Test vector abc=011 or 111 Test c s-a-1 Set c=0 Make f sensitive to c b=1 Test vector abc=010 or 110

Solution: part (d)  Initialized to 0 and fed with (MSB first ).  What is 4-input XOR?

XOR gates abcdout a b c d a b c d Output is high when odd number of inputs is high

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Part (d): 5 th bit in error  Fed with (MSB first ). InputTest

Part (d): 5 th bit in error  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest

Solution: part (d)  Fed with (MSB first ). InputTest  Signature is different  This fault is detected