Research Progress Seminar

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Research Progress Seminar Hardware and Software Optimization of BABSMOM System FIR Filter s1150072 Yumiko Kimezawa June 7, 2010 RPS

Outline Digital filter FIR filter Why is an FIR filter used ? Structure of an FIR filter Data flow diagram Future work June 7, 2010 RPS

Graphic LCD Controller ADC 1 ADC 12 FIR 1 FIR 12 Buffer ECG Signal Analysis External Memory 1:Signal reading 2:Filtering 3:Analysis P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms 4:Display Raw ECG/EKG Data ROM Virtual External Memory LED Controller Graphic LCD Controller Slave CPU Slave CPU Memory Timer Master CPU Master Shared FIR Filter Graphic LCD JTAG UART PPD Module Master Module June 7, 2010 RPS

Digital filter Digital filter Mathematical processing to digital signal Noise rejection Waveform extraction There are two main types of a digital filter are FIR filter Finite Impulse Response filter IIR filter Infinite Impulse Response filter This ECG/EKG system uses an FIR filter. June 7, 2010 RPS

FIR filter FIR filter One of the ways to configure a digital filter A liner phase an oscillation does not happen Inherent stability a distortion of waveform does not happen Impulse response is finite June 7, 2010 RPS

Why is an FIR filter used ? The data from analog/digital converter is finite and discrete digital signal. This ECG/EKG system use FIR filter. June 7, 2010 RPS

Structure of an FIR filter An FIR filter is shown by the following difference equation. : Input signals It shows the way to process signals. FIRフィルタは、次の差分方程式で表現される。 この式で、x[n]は入力信号、y[n]は出力信号。 aiはフィルタの係数。この係数でフィルタの周波数特性が決まる。この係数はインパルス応答に対応する。 また、Nはこのフィルタの次数。これはタップ(サンプリングの数)の数に対応する。 この差分方程式は、信号の処理方法を表してると考えてもいい。 ----- インパルス応答 サンプリング …アナログ信号の強 さを一定時間ごとに採取し、デ ジタル記録が可能な形にすること。 : Output signals : Filter order : Filter coefficient June 7, 2010 RPS

Data flow diagram The FIR filter is composed of three parts. Figure: The basic block diagram for an FIR filter of N order. この図はN次のFIRフィルタの一般的なブロック図である。 FIRフィルタは遅延器、乗算器、加算器で構成されている。 June 7, 2010 RPS

Data flow diagram Delay element - temporal delay - delay signal for one clock for sampling 遅延器: 時間的な遅延を意味する。 サンプリングの1周期(1クロック)だけ信号を遅延する素子。 X(n-2)はX(n-1)より時間的に1つ前のデータ、X(n-1)はX(n)より時間的にひとつ前のデータになる。 June 7, 2010 RPS

Data flow diagram June 7, 2010 RPS

Data flow diagram Multiplier - multiply filter coefficient by an input signal 乗算器: 入力信号に係数倍する。 June 7, 2010 RPS

Data flow diagram June 7, 2010 RPS

Data flow diagram Adder -Add output result from all multiplier 加算器: 全ての乗算器からの結果を足し合わせ出力する。 入力x[n]にはサンプリングされたデジタルデータが次々に入ってくる。 出力データはそのたびに出力される。 June 7, 2010 RPS

Difference equation : Filter order An FIR filter is shown by the following difference equation. : Input signals : Output signals : Filter order FIRフィルタのブロック図の動作を表すFIRフィルタの差分方程式。 : Filter coefficient June 7, 2010 RPS

Future work Understand current ECG Algorithm Pam Tompskins Understand new algorithm developed last year Period-Peak Detection (PPD) Algorithm June 7, 2010 RPS