MEMORY GENERATORS MEMPRO Instructor: Dr. Anthony Johnson Presented by: Rajesh Natarajan Motheeswara Salla

Overview Of The Mempro Memory Design Tool Mempro generates high performance verilog or VHDL memory Models on demand. Quick redesign options. Comparison of various designs. Built-in self test control features. Generates system memory up to 64-bit addresses and data bus widths up to 2048.

Design Of Memory Model In Mempro Mempro Graphics Interface (Defines Memory Device Characteristics) Definition Page Configuration Page Ports Page Timing Page

DESIGN OF A MEMORY MODEL IN MEMPRO(contd...) Four MemSpec pages define the memory device characteristics that are modeled Definition – Defines memory class,size,model name and title,along with embedded HDL comments Configuration – Defines specific memory architecture within a memory class. Ports – Defines port names and characteristics. Timing-Defines timing parameters modeled,their names and values. You can quickly create families of models by editing existing specifications files

Definition Page Options Available In Definition Page Definition Page User Interface Memory Type (Class) Addr Width Model Name Data Width Memory TitleDocumentation

Definition Page(Contd...) Memory Model definitions

Definition Page(contd...)

Configuration Page The configuration page is used to define characteristics or features of the specific memory class that was selected on the definition page This page is memory class dependent i.e. The feature selections vary depending on the selected memory class.

Configuration Page(contd...) Configuration page for Dram Memory Class

Ports Page The ports page lets you define model attributes. Ports page attributes Port namesPolaritiesBus namesX checkingPort function

Ports Page (Contd…) Port Attribute Descriptions

Ports Page (Contd…) Ports page parameters for Dram memory class

Timing Page 1. The timing page specifies timing constraint and delay information for a model. 2.The timing page supports maximum,minimum and typical values. 3.This page is memory class (type) dependent.

Timing Page (Contd…) Timing Constraints A timing constraint is relationship between two events.The model checks the time relationship to make sure the minimum or maximum time between the events has not been violated.An example of a timing constraint is setup and hold times,that is,the time a signal must be stable before and after signal changes. Timing delays A timing delay is the time the model waits before changing a signal, such as the delay from an enable signal becoming active until affected signals change from high impedance to valid data states.

Timing Page (Contd…) Timing Attribute Descriptions Timing page attributes LabelTypeUnitsValuescomments

Timing Page (Contd…) Timing page parameters for Dram memory class

Building a Memory Model Graphical user interface (to define model characteristics and Usage environment) Finish page Option page

The options page Mempro creates HDL memory models by the specifications on the first four pages. The options page specifies the features of the model itself ;not memory. Option page attributes LanguageMessagesLogic statesSimulatorInitializationStorage type

Options Page (Contd…) Memory Model Build Options 1. Simulation language 10.Bit Blast Option 2. Timing unit 11.Message settings 3. Timing precision 12.Show error messages 4. Target simulator 13.Show warning messages 5. Timing option 14.Show info messages 6. Timing range 15.Show timing messages 7. Timing version 16.Show X-handling messages 8. Storage type 17.Memory default value 9. X checking option 18.Memory init file

The Options Page (Contd..) Options page Dram parameters example

The Finish Page The finish page shows the finally saved specification and model attributes. Finish page Dram parameters example

Finish Page (Contd…) 1. The “Save memory specification” option saves the memory specification file, using the current filename. 2. The “Built memory model”creates the specified memory model file using the model name specified on the definition page as the root filename. 3.The “Generate Test bench”prompts you to enter a test bench filename.

Automated Test bench Creation The test bench contains the behavioral architecture of the model including the stimulus applied to each input port and a generated results check.

Memory Mapping Memory Mapping Methods Device Mapping Masked Mapping Interleaved Mapping Sliced and Interleaved Mapping Sliced Mapping Masked and Interleaved Mapping

Device Mapping

Sliced Mapping

Interleaved Mapping

Sliced and Interleaved Mapping

Masked Mapping

Masked and Interleaved

User Interface for Memory Mapping

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