M.Mohajjel

Objectives Learn How to write synthesizable Verilog code Common mistakes and how to avoid them What is synthesized for what we code Digital System Design2

Logic Synthesis Why? Definition process of converting a high-level description of the design into an optimized gate-level representation, given a standard cell library and certain design constraints Digital System Design3

Logic Synthesis (cont.) RTL to gate level Behavioral Synthesis (High Level Synthesis) Decide number of registers and their interconnects in addition to RTL synthesis Digital System Design4

Logic Synthesis (cont.) Behavioral Synthesis (High Level Synthesis) Scheduling Allocation Mapping Digital System Design5 Source:

Logic Synthesis (cont.) Behavioral Synthesis (High Level Synthesis) Example Digital System Design6 PROCEDURE Test; VAR A,B,C,D,E,F,G:int eger; BEGIN Read(A,B,C,D,E); F := E*(A+B); G := (A+B)*(C+D);... END; Input behavioral specification

Logic Synthesis (cont.) Behavioral Synthesis (High Level Synthesis) Example Digital System Design7 PROCEDURE Test; VAR A,B,C,D,E,F,G:int eger; BEGIN Read(A,B,C,D,E); F := E*(A+B); G := (A+B)*(C+D);... END; Input behavioral specification

Logic Synthesis (cont.) Behavioral Synthesis (High Level Synthesis) Example Digital System Design8 Data-path allocation Control allocation

Traditional Logic Design Flow Design constraints Timing Area Power … Digital System Design9 Limitations Human errors Time overhead

Logic Design Flow Digital System Design10

Computer-Aided Logic Design Flow Translation Logic optimization Technology mapping and optimization Digital System Design11

Computer-Aided Logic Design Flow (cont.) Technology library Functionality Area Timing Power Design constraints Timing Area Power Digital System Design12

An Example of RTL-to-Gates module magnitude_comparator(A_gt_B, A_lt_B, A_eq_B, A, B); output A_gt_B, A_lt_B, A_eq_B; input [3:0] A, B; assign A_gt_B = (A > B); assign A_lt_B = (A < B); assign A_eq_B = (A == B); endmodule Digital System Design13 RTL description

An Example of RTL-to-Gates (cont.) //Library cells for abc_100 technology VNAND//2-input nand gate VAND//2-input and gate VNOR//2-input nor gate VOR//2-input or gate VNOT//not gate VBUF//buffer NDFF//Negative edge triggered D flip-flop PDFF//Positive edge triggered D flip-flop Digital System Design14 Technology library

An Example of RTL-to-Gates (cont.) Digital System Design15 Final, Optimized, Gate-Level Schematic

An Example of RTL-to-Gates (cont.) Digital System Design16 Final, Optimized, Gate-Level Description module magnitude_comparator ( A_gt_B, A_lt_B, A_eq_B, A, B ); input [3:0] A; input [3:0] B; output A_gt_B, A_lt_B, A_eq_B; wire n60, n61, n62, n50, n63, n51, n64, n52, n65, n40, n53, n41, n54, n42, n55, n43, n56, n44, n57, n45, n58, n46, n59, n47, n48, n49, n38, n39; VAND U7 (.in0(n48),.in1(n49),.out(n38) ); VAND U8 (.in0(n51),.in1(n52),.out(n50) ); VAND U9 (.in0(n54),.in1(n55),.out(n53) ); VNOT U30 (.in(A[2]),.out(n62) ); VNOT U31 (.in(A[1]),.out(n59) ); VNOT U32 (.in(A[0]),.out(n60) ); VNAND U20 (.in0(B[2]),.in1(n62),.out(n45) ); VNAND U21 (.in0(n61),.in1(n45),.out(n63) ); …. VNAND U18 (.in0(n56),.in1(n55),.out(n51) ); VNAND U19 (.in0(n50),.in1(n44),.out(n61) ); VAND U2 (.in0(n38),.in1(n39),.out(A_eq_B) ); VNAND U3 (.in0(n40),.in1(n41),.out(A_lt_B) ); VNAND U4 (.in0(n42),.in1(n43),.out(A_gt_B) ); VAND U5 (.in0(n45),.in1(n46),.out(n44) ); VAND U6 (.in0(n47),.in1(n44),.out(n39) ); endmodule

An Example of RTL-to-Gates (cont.) module stimulus; reg [3:0] A, B; wire A_GT_B, A_LT_B, A_EQ_B; magnitude_comparator MC(A_GT_B, A_LT_B, A_EQ_B, A, B); initial $monitor($time," A = %b, B = %b, A_GT_B = %b, A_LT_B = %b, A_EQ_B = %b", A, B, A_GT_B, A_LT_B, A_EQ_B); initial begin A = 4'b1010; B = 4'b1001; # 10 A = 4'b1110; B = 4'b1111; # 10 A = 4'b0000; B = 4'b0000; # 10 A = 4'b1000; B = 4'b1100; # 10 A = 4'b0110; B = 4'b1110; # 10 A = 4'b1110; B = 4'b1110; end endmodule Digital System Design17

An Example of RTL-to-Gates (cont.) Simulation Library //Simulation Library abc_100.v. Extremely simple. No timing checks. module VAND (out, in0, in1); input in0; input in1; output out; //timing information, rise/fall and min:typ:max specify (in0 => out) = ( : : , : : ); (in1 => out) = ( : : , : : ); endspecify //instantiate a Verilog HDL primitive and (out, in0, in1); endmodule... //All library cells will have corresponding module definitions //in terms of Verilog primitives.... Digital System Design18

Modeling Tips for Logic Synthesis Avoid mixing positive and negative edge-triggered flipflops Be careful with multiple assignments to the same variable clk) if(load1) q <= a1; clk) if(load2) q <= a2; Digital System Design19

Modeling Tips for Logic Synthesis (cont.) Use parentheses to optimize logic structure out = a + b + c + d; out = (a + b) + (c + d) ; Digital System Design20

Modeling Tips for Logic Synthesis (cont.) Define if-else or case statements explicitly level-sensitive latches may be inferred Digital System Design21 case ({a,b}) 2’b10 : out=1; 2’b01 : out=0; endcase case ({a,b}) 2’b10 : out=1; 2’b01 : out=0; default: out=0; endcase Out=0; case ({a,b}) 2’b10 : out=1; 2’b01 : out=0; endcase

Modeling Tips for Logic Synthesis (cont.) Digital System Design22

Modeling Tips for Logic Synthesis (cont.) Can't mix posedge/negedge use with plain signal references Digital System Design23 module DFF_bad (clk, reset, d, q); input clk,reset,d; output reg q; clk or reset) begin if (reset) q <= 1'b0; else q <= d; end endmodule

Modeling Tips for Logic Synthesis (cont.) Use nonblocking assignment for sequential always block Use blocking assignment for combinational always block Digital System Design24 clk) begin q1=d; q2=q1; q=q2; end clk) begin q1<=d ; q2<=q1; q <=q2; end

Modeling Tips for Logic Synthesis (cont.) Temporal loop in the body Not recommended Spatial loop or i2) for(k=0; k<2; k=k+1) out[k] = i1[k] & i2[k]; endmodule Digital System Design25

Modeling Tips for Logic Synthesis (cont.) Spatial loop (cont.) module syn (output reg [2:0] matchCount = 0, input [6:0] message, pattern); integer i; begin for (i = 0; i < 7 ; i = i + 1) matchCount = matchCount + ~(message[i] ^ pattern[i]); end endmodule Digital System Design26

Modeling Tips for Logic Synthesis (cont.) Spatial loop (cont.) Digital System Design27

Synthesizable Codes Structural & Dataflow Models Delays (#) are ignored Behavioral Models Synthesizability is restricted to a subset Digital System Design28

Synthesizable Behavioral Models initial is not supported While and forever loops must clk) clk) Not recommended Digital System Design29