1 COMP541 State Machines – 2 Registers and Counters Montek Singh Feb 11, 2010

Topics  Lab preview  Verilog styles for FSM Don’t forget to check synthesis output and console msgs. Don’t forget to check synthesis output and console msgs.  State machine styles Moore vs. Mealy Moore vs. Mealy  Building blocks: registers and counters 2

Lab Preview: Buttons and Debouncing  Button normally high press pulls it low press pulls it low  Mechanical switches “bounce” vibrations cause them to go to 1 and 0 a number of times vibrations cause them to go to 1 and 0 a number of times hundreds of times! hundreds of times!  We’ll want to “Debounce”: Any ideas? “Debounce”: Any ideas? Synchronize with clock Synchronize with clock  Think about: What does it mean to “press the button”? Think carefully!! What does it mean to “press the button”? Think carefully!! What if button is held down for a long time? What if button is held down for a long time? 3

Verilog Styles for FSM  Try to explain what synthesizer is doing Read the messages on the console Read the messages on the console 4

Pitfall: Beware of Unexpected Latches!  You can easily specify latches unexpectedly Hangover from programming in C…! Hangover from programming in C…!  always will try to synthesize FF: if (select) out <= A; if (!select) out <= B; FF added to save old value if condition is false FF added to save old value if condition is false  To avoid extra FF, cover all possibilities: if (select) out <= A; else out <= B; 5

FSM Verilog: Using One Always Block clk) begin case (state) case (state) s1: if (x1 == 1'b1) begin s1: if (x1 == 1'b1) begin state <= s2; outp <= 1'b1; state <= s2; outp <= 1'b1; end end else begin else begin state <= s3; outp <= 1'b0; state <= s3; outp <= 1'b0; end end s2: begin state <= s4; outp <= 1'b1; state <= s4; outp <= 1'b1; end end s3: begin s3: begin state <= s4; outp <= 1'b0; state <= s4; outp <= 1'b0; end end s4: begin s4: begin state <= s1; outp <= 1'b0; state <= s1; outp <= 1'b0; end end endcase endcaseend 6 ~x1

Synthesis Output Synthesizing Unit. Related source file is "v_fsm_1.v". Related source file is "v_fsm_1.v". Found finite state machine for signal. Found finite state machine for signal | States | 4 | | States | 4 | | Transitions | 5 | | Transitions | 5 | | Inputs | 1 | | Inputs | 1 | | Outputs | 4 | | Outputs | 4 | | Clock | clk (rising_edge) | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset type | asynchronous | | Reset State | 00 | | Reset State | 00 | | Power Up State | 00 | | Power Up State | 00 | | Encoding | automatic | | Encoding | automatic | | Implementation | LUT | | Implementation | LUT | Found 1-bit register for signal. Found 1-bit register for signal. Summary: Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). 7

Split Output Off  Separate always for outp 8

Code clk) case (state) case (state) s1: if (x1 == 1'b1) s1: if (x1 == 1'b1) state <= s2; state <= s2; else else state <= s3; state <= s3; s2: state <= s4; s2: state <= s4; s3: state <= s4; s3: state <= s4; s4: state <= s1; s4: state <= s1; endcase endcase case (state) s1: outp <= 1'b1; s1: outp <= 1'b1; s2: outp <= 1'b1; s2: outp <= 1'b1; s3: outp <= 1'b0; s3: outp <= 1'b0; s4: outp <= 1'b0; s4: outp <= 1'b0; endcase endcase 9

Synthesis (no latch) Synthesizing Unit. Related source file is "v_fsm_2.v". Related source file is "v_fsm_2.v". Found finite state machine for signal. Found finite state machine for signal | States | 4 | | States | 4 | | Transitions | 5 | | Transitions | 5 | | Inputs | 1 | | Inputs | 1 | | Outputs | 1 | | Outputs | 1 | | Clock | clk (rising_edge) | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset type | asynchronous | | Reset State | 00 | | Reset State | 00 | | Power Up State | 00 | | Power Up State | 00 | | Encoding | automatic | | Encoding | automatic | | Implementation | LUT | | Implementation | LUT | Summary: Summary: inferred 1 Finite State Machine(s). Unit synthesized. 10

Textbook Uses 3 always Blocks 11

Three always Blocks clk) clk) begin begin state <= next_state; end end or x1) or x1) begin begin case (state) case (state) s1: if (x1==1'b1) s1: if (x1==1'b1) next_state <= s2; next_state <= s2; else else next_state <= s3; next_state <= s3; s2: next_state <= s4; s2: next_state <= s4; s3: next_state <= s4; s3: next_state <= s4; s4: next_state <= s1; s4: next_state <= s1; endcase endcase end end begin begin case (state) case (state) s1: outp <= 1'b1; s1: outp <= 1'b1; s2: outp <= 1'b1; s2: outp <= 1'b1; s3: outp <= 1'b0; s3: outp <= 1'b0; s4: outp <= 1'b0; s4: outp <= 1'b0; endcase endcase end end 12

Synthesis (again, no latch) Synthesizing Unit. Related source file is "v_fsm_3.v". Related source file is "v_fsm_3.v". Found finite state machine for signal. Found finite state machine for signal | States | 4 | | States | 4 | | Transitions | 5 | | Transitions | 5 | | Inputs | 1 | | Inputs | 1 | | Outputs | 1 | | Outputs | 1 | | Clock | clk (rising_edge) | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset type | asynchronous | | Reset State | 00 | | Reset State | 00 | | Power Up State | 00 | | Power Up State | 00 | | Encoding | automatic | | Encoding | automatic | | Implementation | LUT | | Implementation | LUT | Summary: Summary: inferred 1 Finite State Machine(s). Unit synthesized. 13

My Preference  The one with 2 always blocks  Less prone to error than 1 always  Easy to visualize the state transitions 14

State Encoding  So far we’ve used binary encoding  Not necessarily best XST chooses one to minimize hardware XST chooses one to minimize hardware  Can change by right-clicking Synthesize-XST Possible encodings next slides Possible encodings next slides 15

Gray Code (synthesis output) ============================================================ * Advanced HDL Synthesis * ============================================================ Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding State | Encoding State | Encoding | | | | | | | |

One-Hot Encoding Optimizing FSM on signal with one-hot encoding State | Encoding State | Encoding | | | | | | | | Hmmm, state register grew. What’s up?

Safe Implementation Mode “XST can add logic to your FSM implementation that will let your state machine recover from an invalid state. If during its execution, a state machine gets into an invalid state, the logic added by XST will bring it back to a known state, called a recovery state. This is known as Safe Implementation mode.” from XST manual “XST can add logic to your FSM implementation that will let your state machine recover from an invalid state. If during its execution, a state machine gets into an invalid state, the logic added by XST will bring it back to a known state, called a recovery state. This is known as Safe Implementation mode.” from XST manual 18

Moore vs. Mealy FSMs?  So, is there a practical difference? 19

Moore vs Mealy Recognizer Mealy FSM: arcs indicate input/output

Moore and Mealy Timing Diagram

Moore vs. Mealy FSM Schematic  Moore  Mealy

23 Registers and Counters: Definitions  Register – a set of flip-flops May include extensive logic to control state transition May include extensive logic to control state transition  May allow shifting register also refers to fast memory for storing data in a computer register also refers to fast memory for storing data in a computer  Counter Register that goes through sequence of states as it is clocked Register that goes through sequence of states as it is clocked

Simple Register  Store D  On posedge of Clock  Clear signal normally high Power-up reset Power-up reset  Symbol 24

Clocking  Typically don’t want to load every clock  Can gate the clock But added clock skew is a problem But added clock skew is a problem 25

Enable  If load H, then D is gated through  Otherwise, Q is fed back Keep same value Keep same value  No clock gating 26  Did this because D FF doesn’t have a “no change” behavior

Counters  Counter is a register – has state  Also goes through sequence of states – counts – on clock or other pulses  Binary counter Counts through binary sequence Counts through binary sequence n bit counter counts from 0 to 2 n n bit counter counts from 0 to 2 n 27

Ripple Counter  Simple  So Q will alternate 1 and 0  Why called ripple counter? 28

Synchronous Counters  Ripple counter is easy rippling nature may cause problems, though rippling nature may cause problems, though  delay increases with bit width!  Synchronous counter most common meaning every flip-flop is driven by the same clock meaning every flip-flop is driven by the same clock 29

Synchronous Counter  Same clock fed to all flip-flops But… But…  delay again increases with bit width 30

Parallel Design  Now “constant” delay higher order bits need gates with more fan-in though higher order bits need gates with more fan-in though  Can gang these to make longer serial-parallel counter 31

Verilog Counter (simple) module count (CLK, EN, Q); input CLK, EN; output [3:0] Q; reg [3:0] Q; CLK) begin if (EN) Q <= Q + 4'b0001; Q <= Q + 4'b0001;endendmodule 32

Verilog Counter (from book) module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] Q; assign CO = (count == 4'b1111 && EN == 1’b1) ? 1 : 0; CLK or posedge RESET) begin if (RESET) Q <= 4'b0000; Q <= 4'b0000; else if (EN) Q <= Q + 4'b0001; Q <= Q + 4'b0001;endendmodule 33

Arbitrary Count  One more type of counter is useful  Count an arbitrary sequence maybe you need a sequence of states maybe you need a sequence of states maybe a pseudo-random sequence maybe a pseudo-random sequence 34

Circuit and State Diagram 35

Shift Registers  Capability to shift bits In one or both directions In one or both directions  Why? Part of standard CPU instruction set Part of standard CPU instruction set Cheap multiplication Cheap multiplication Serial communications Serial communications  Just a chain of flip-flops 36

Simple 4-Bit Shift Register  Clocked in common  Just serial in and serial out  Is this a FIFO? 37

Verilog for Simple 4-bit Shift Register module srg_4_r (CLK, SI, Q, SO); input CLK, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; CLK) begin Q <= {Q[2:0], SI}; Q <= {Q[2:0], SI};endendmodule 38

Symbol  How about enabling/disabling? We could gate the clock We could gate the clock  But have to potentially deal with skew Usually an enable provided Usually an enable provided 39

Parallel Load  Can provide parallel outputs from flip-flops  And also parallel inputs 40

Schematic 41 Detail Next

Detail 42

Why is this useful?  Basis for serial communications  Keyboard  Serial port Initially to connect to terminals Initially to connect to terminals Now mainly for modem Now mainly for modem  USB  Firewire 43

Example 44 Clocked 4 times Could shift data in, or parallel load What’s on wire at each clock?

Table Showing Shift 45

Serial vs. Parallel Transfer  Parallel transfer – over as many wires as word (for example)  Serial transfer – over a single wire Trade time for wires Trade time for wires Takes n times longer Takes n times longer  although lately, may have speed advantages over parallel in very high-speed scenarios  e.g., USB (Universal Serial Bus) 46

Bidirectional Shift Register  Shift either way  Now we have following possible inputs Parallel load Parallel load Shift from left Shift from left Shift from right Shift from right Also “no change” Also “no change”  Schematic next 47

Schematic 48

Next Week  How to generate a VGA signal  Timing of sequential logic  Then on to Arithmetic circuits Arithmetic circuits Memories Memories 49