EKT 121 / 4 DIGITAL ELECTRONICS 1 Chapter 2: Combinational Logic Circuits

2.1 Combinational Logic Analysis Basic Combinational Logic Circuits Implementing Combinational Logic The Universal Property of NAND and NOR gates

The AND-OR Logic

The AND-OR-Invert Logic

The Exclusive-OR logic How about Ex-NOR logic???

X-Nor Equation

a) Gate Symbol, Boolean Equation Exclusive-OR Gate a) Gate Symbol, Boolean Equation & Truth Table b) Timing Diagram

Ex-OR and Ex-NOR

Implementing Combinational Logic From Boolean Expression to Logic Circuit From Truth Table to Logic Circuit

The NAND and NOR gates as Universal Logic Elements Both the NAND and NOR gates are universal gates because they can each represent the NOT, AND, OR and NOR functions.

The Universal NAND gate

The Universal NOR gate

Equivalence Symbols NAND NOR Please sketch !!

2.2 Functions of Combinational Logic Basic Adders Parallel Binary Adder Ripple Carry Adder Comparators Decoders Encoders

2.2 Functions of Combinational Logic Code Converters Multiplexers (Data Selectors) Demultiplexers Parity Generators/ Checkers

Decoders & Encoders

Encoder Encoder converts information such as decimal number or an alphabetical character into some binary coded form Encoder is usually used for: Data representation Data security Data compression

Encoder Example: 8-to-3 Binary Encoder Only one of the inputs can be 1.

Design Exercise Write the equations for Y2, Y1 and Y0. Draw the logic circuit to implement this 8-to-3 encoder.

The decimal-to-BCD Encoder

Decoder A decoder is a circuit that creates an output based on the binary states of a given input Selects 1 of several output lines, based on a coded input signal. Do the opposite of encoder

Decoder Example: 3 to 8 Binary Decoder The inputs are treated as a binary number and the output selected is made active.

A 4-line-to-16-line Decoder

The BCD-to-decimal Decoder

The BCD to 7-segment Decoder Accepts BCD code on inputs and provide outputs to drive 7-segment display devices to produce a decimal readout.

BCD to 7-Segment Decoder /Bl D C B A a b c d e f g 0 x x x x 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 -- don’t care inputs -- A BCD to 7-segment decoder has 4-bit BCD input and the seven segment display code as its output: In minimizing the circuits for the segment outputs all non-decimal input combinations (1010, 1011, 1100,1101, 1110, 1111) are taken as don’t-cares

Figure 4–47 Seven-segment display format showing arrangement of segments. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4–48 Display of decimal digits with a 7-segment device. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4–49 Arrangements of 7-segment LED displays. Active-low Active-high Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4–50 Block diagram of 7-segment logic and display. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Design Example From the truth table, an SOP or POS can be written for each segment. Derive an SOP for segment a. Minimize the SOP using a K-map. Draw the logic circuit to implement segment a of the 7-segment display.

Figure 4–51 Karnaugh map minimization of the segment-a logic expression. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4–52 The minimum logic implementation for segment a of the 7-segment display. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

BCD to 7-segment Decoder Application Example:

Lab 3 Use of 74S90 IC, a BCD counter – as inputs to the BCD to 7-segment decoder. Part B Prepare the design before coming to lab! For unused input states, the output is either a ‘0’ or ‘X’. TT, K-map and circuit.

Decoders & Encoders - A Second Look -

Convert numbers to be displayed BCD to 7-segment display decoder Hex to 7-segment display decoder

7-Segment Display Configuration Common Anode Requires logic 0 to light up (ON) a segment. Common Cathode Requires logic 1 to light up (ON) a segment.

m ≤ 2n 3-5 DECODERS m n DECODER Converts binary information, from n coded inputs to a maximum of 2n outputs

3-5 DECODERS To generate the 2n (or less) minterms of input variables. Functional Specs: To generate the 2n (or less) minterms of input variables. For each input, 7 outputs are equal to 0 and only 1 equals to 1. The output that is 1 represents the minterm equivalent of the input number.

Truth Table for 3-to-8-Line Decoder

3-to-8-Line Decoder

A 2-to-4-Line Decoder

Decoder Expansion When a certain decoder size is needed, but only smaller number of sizes is available. Combine 2 or more decoders in a hierarchy, i.e. cascade the smaller decoders to form a larger decoder size.

Example: A 3-to-8 Decoder Constructed with Two 2-to-4 Decoders

… Its Operation Top decoder enabled  Generates minterms D0 to D3. The MSB input, A2, functions: As enable, EN, of one decoder, and As its complement, N(EN) to the other decoder. When A2=0, Top decoder enabled  Generates minterms D0 to D3. Lower decoder disabled  Outputs equal to 0. When A2=1, Top decoder disabled  Outputs equal to 0. Lower decoder enabled  Generates minterms D4 to D7.

… Enable Input For the purpose of expanding digital functions into: Very useful and convenient way to interconnect 2 or more functional blocks. For the purpose of expanding digital functions into: Similar functions with more inputs and outputs.

Exercise Four 4-to-16-line decoders and one 2-to-4-line decoder. Construct a 6-to-64-line decoder, using: Four 4-to-16-line decoders and one 2-to-4-line decoder.

Combinational Circuit Implementation of Decoders Binary Adder

Implementing a Binary Adder Using a Decoder S(X,Y,Z) = m (1, 2, 4, 7) C(X,Y,Z) = m (3, 5, 6, 7) 3 inputs and 8 minterms  Use a 3-to-8 decoder.

Implementing a Binary Adder Using a 3-to-8 Decoder

3-6 ENCODERS ENCODER n m m ≤ 2n

3-6 ENCODERS Inverse operation of decoder. The output lines generate the binary code corresponding to the input value. Assume only 1 input has the value of 1 at any given time. Example: Octal-to-binary encoder.

Truth Table for Octal-to-Binary Encoder

Priority Encoder

What about when 2 inputs are 1 at the same time? Use “Priority Encoder” To ensure only one input is encoded. e.g. D3 = D6 = 1  Output = 110 (D6 has a higher priority than D3)

Priority Encoder … If 2 or more inputs are equal to 1 at the same time, the input having the highest priority is the one encoded. Example: 4-input Priority Encoder Use condensed TT (5 rows to represent 16 rows). V (valid) =1 when 1 or more input is equal to 1.

Condensed Truth Table of Priority Encoder X @ output => don’t care X @ input => product term that is not minterm

Maps for Priority Encoder

Logic Diagram of a 4-Input Priority Encoder

Functions of Combinational Logic Adder Encoder Comparator Decoder Multiplexer Demultiplexer Parity Generator Parity Checker Code Converters

ADDERS Half Adder Full Adder

Half Adder X 1 Y S C-out Half Adder Truth Table: S(X,Y) =  (1,2) Adding two single-bit binary values, X, Y produces a sum S bit and a carry out C-out bit. This operation is called half addition and the circuit to realize it is called a half adder. X 1 Y S C-out Half Adder Truth Table: Inputs Outputs S(X,Y) =  (1,2) S = X’Y + XY’ S = X  Y C-out(x, y, C-in) =  (3) C-out = XY X Y Sum S C-out Circuit Half Adder X Y S C-OUT Block diagram/ Symbol/ Black- box view

Full Adder Full Adder Truth Table X 1 Y S C-out C-in Sum S C-in X 1 00 01 11 10 Y XY 2 3 6 7 4 5 Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit. Full Adder Truth Table X 1 Y S C-out C-in S(X,Y, C-in) =  (1,2,4,7) C-out(x, y, C-in) =  (3,5,6,7) Inputs Outputs S = X’Y’(C-in) + X’Y(C-in)’ + XY’(C-in)’ + XY(C-in) S = X  Y  (C-in) C-in X 1 00 01 11 10 Y XY 2 3 6 7 4 5 Carry C-out C-out = XY + X(C-in) + Y(C-in)

Full Adder Full Adder Circuit Using AND-OR: Circuit Block diagram Full XY YC-in C-out XC-in X Y C-in X’Y’C-in XY’C-in’ Sum S X’YC-in’ XYC-in X’ Y’ C-in’ Circuit X X’ Y Y’ C-in C-in’ Full Adder X Y S C-in C-out Block diagram

Full Adder Full Adder Circuit Using XOR: Full Adder C-out Sum S X Y S YC-in C-out XC-in X Y C-in Sum S Full Adder X Y S C-in C-out

HA`and `FA symbols

Arrangement of 2 half-adders to form a full-adder CASCADE

Exercise: Determine the output values

2-Bit Parallel Adder

Determine the sum of this 3-bit parallel Adder

4-bit Parallel Adder

Bigger Adders 8-bit using two 4-bit Adders 16-bit using four

Larger Adders Example: 16-bit adder using 4, 4-bit adders Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position. 4-bit Adder C-in C-out C0 =0 C4 C8 C12 C16 Data inputs to be added X (X0 to X15) , Y (Y0-Y15) Sum output S (S0 to S15) Y3Y2Y1Y0 X3X2X1X0 S3 S2 S1 S0 Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 n x8 or 32 gate delays

A 4-bit parallel ripple carry adder Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

n-bit Carry Ripple Adders An n-bit adder used to add two n-bit binary numbers can built by connecting in series n full adders. Each full adder represents a bit position j (from 0 to n-1). Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1. The output of a full adder at position j is given by: Sj = Xj  Yj  Cj Cj+1 = Xj . Yj + Xj . Cj + Y . Cj In the expression of the sum Cj must be generated by the full adder at the lower position j-1. The propagation delay in each full adder to produce the carry is equal to two gate delays = 2  Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately: Total Propagation delay = 2 n

4-bit Ripple Carry Adder X3X2X1X0 S3 S2 S1 S0 C-in C-out C4 Y3Y2Y1Y0 C0 =0 Inputs to be added Sum Output Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3 Total Propagation delay = 2 n8 or 8 gate delays Full Adder X1 Y1 S1 C-in C-out X0 Y0 S0 C0 =0 X2 Y2 S2 X3 Y3 S3 C1 C2 C3 C4 Data inputs to be added Sum output Cascade 4 full adders to get a 4-bit full adder

Other types of Parallel Adders Carry Look-Ahead Carry-Select Adder Carry-Save Adder Etc.

1’s Complement and 2’s Complement Hardware The 2’s complement of a binary number is formed by adding 1 to the 1’s complement. 2’s complement = (1’s complement) + 1

How to use an adder as a Subtractor?

Building a Subtractor using an Adder and 2’s Complement (for positive numbers) A – B = A + (-B) = A + B + 1 To perform subtraction using an adder, we invert B, and use Cin =1. 2’s complement Try drawing this diagram…

Other types of Parallel Adders Carry Look-Ahead Carry-Select Adder Carry-Save Adder Etc.

ADDERS – A Second Look -

Adders and its Applications Subtractor Multipliers Dividers

ARITHMETIC CIRCUITS Is a combinational circuit that performs arithmetic operations, e.g. Addition Subtraction Multiplication Division with numbers in binary form.

Half Adder Generates the sum of 2 binary digits. Sum = X  Y Cy = X.Y

Truth Table of Half Adder

Logic Diagram of Half Adder

Full Adder Forms the arithmetic sum of 3 input bits. Sum = X  Y  Z Cout = X.Y + Z (X  Y) Cin

Truth Table of Full Adder

K-Maps for Full Adder

Full Adder A Full Adder can also be implemented using 2 HALF ADDERS and one OR gate. Cascade two half adders (Array method) Design “Smart”

Full Adder (Array Method) Design “Smart”

1’s Complement and 2’s Complement Hardware The 2’s complement of a binary number is formed by adding 1 to the 1’s complement. 2’s complement = (1’s complement) + 1

How to use an adder as a Subtractor?

Building a Subtractor using an Adder and 2’s Complement (for positive numbers) A – B = A + (-B) = A + B + 1 To perform subtraction using an adder, we invert B, and use Cin =1. 2’s complement Try drawing this diagram…

2-bits x 2-bits Multiplier Design Exercise 2-bits x 2-bits Multiplier

Terms Mutiplicand Multiplier Product 2 X 3 -------------- 6

Multiplication in binary form? Rewrite the multiplication in binary form. Sketch the black box view. The multiplier multiplies two __?__ bits numbers.

2-bits x 2-bits Multiplier Design Two techniques: Using the standard K-Map Using Arrays (cascaded approach)

Method A: Using the K-Map Technique Sketch the bLack box. Sketch the Truth Table for a 2-bit “multiplier” and 2- bit “multiplicand”. Input (Multiplier) = A1 and A0 Input (Multiplicand) = B1 and B0 Output (4-bits) = S3, S2, S1 and S0 or S[3..0] Using K-Maps, obtain the boolean expression for each output. Sketch the schematic diagram.

Method B: Using the Array (Cascaded) Technique Create the 2x2 multiplier using Full ADDERS. Design “Smart”

… tHE cONcEpt A1 A0 B1 B0 x C C A1B0 A0B0 + A1B1 A0B1 S3 S2 S1 S0

A 2-Bit by 2-Bit Binary Multiplier

Half adder computes sum. Will need FA for larger multiplier. AND computes A0 B0 Half adder computes sum. Will need FA for larger multiplier. 105

The 4-bits x 4-bits Multiplier Using Array 2x2

Basic Idea of a Larger Multiplier (4-bits by 3-bits)

Multiplier Product The product of m-bit x n-bit numbers is an (m+n)-bit number. => The product of two 4-bit numbers is an 8-bit number. 108

13 X 11 -------------- 143 Mutiplicand Multiplier Product How about this one? Mutiplicand Multiplier Product 13 X 11 -------------- 143

1 (143) Product (11) multiplier X (13) multiplicand Partial products

S0 S1 S2 S3 S4 S5 S6 S7 A0B3 A1B3 A2B3 A3B3 A0B2 A1B2 A2B2 A3B2 A0B1 A1B1 A2B1 A3B1 A0B0 A1B0 A2B0 A3B0 B0 B1 B2 B3 A0 A1 A2 A3

From the previous slide: The multiplier multiplies two __?__ bits numbers. Sketch the black box view.

Design a 4-bits x 4-bits multiplier using the Array (cascaded) technique, by utilizing: The 2-bits x 2-bits Multiplier and full adder designed earlier. Hints : Look back at the concept of 2x2 multiplier. Take the same step.

4x4 Combinational Multiplier Note use of parallel carry-outs to form higher order sums 12 Adders, if full adders, this is 6 gates each = 72 gates 16 gates form the partial products total = 88 gates! 114

Array Multiplier 1 building block 4 x 4 array of building blocks 115

4x4 Tenth & Unit Multiplier Segment (your design) Decoder a - g Pin Configuration to input (use flex switch 1-8) Pin Configuration to output (use flex digit 1 & 2 ) 4x4 Multiplier (your design) Tenth & Unit Segment Decoder 7447 BCD to 7Seg a - g A0 A1 A2 A3 B0 B1 B2 B3

Functions of Combinational Logic Adder Encoder Comparator Decoder Multiplexer Demultiplexer Parity Generator Parity Checker Code Converters

Equality Comparator Inequality Comparator

Equality Comparator To compare two binary strings (or binary words) to determine if they are exactly equal. Truth table for a comparator: What is the Boolean expression for this truth table? Can you draw the circuit for basic comparator? A B A=B 0 0 1 0 1 0 1 0 0 1 1 1

Equality Comparator Comparing two binary strings (or binary words) to determine if they are exactly equal. Truth table for a comparator: 1-bit comparator A B A=B 0 0 1 0 1 0 1 0 0 1 1 1 A=B is same as output for Ex-NOR gate

Basic Equality Comparator Operation

1-bit Comparator with Inequality outputs To compare 2 binary numbers, each 1-bit wide. The result of the comparison are single bit outputs that indicate whether the numbers are equal to each other, or if one number is greater than or less than another. A=B ? A<B? A>B?

Design Exercise For the comparator explained in the previous slide , Derive its truth table. Minimize the output equations using K-maps. Draw the logic circuit.

2-bit Comparator Sketch the black box view/ symbol Produce the truth table Use K-maps Sketch the circuit

Design Exercise Repeat the previous design exercise for a 4- bit comparator with inequality outputs.

4-bit Comparator with Inequality Indication

8- bit Comparator To design a comparator to evaluate two 4 bit numbers, we need 4 Ex-NORs and a 4-input AND gate 8 bit magnitude comparator (cascade two 4-bit comparators):

Code Converters

Code Converters A device that converts data in one type of code and produces an output expressed in another type. Example, BCD to binary, BCD to 7-segment display, Gray-to-binary code and binary-to- Gray code. Still remember…………………………….? Binary code vs Gray Code. To convert binary to Gray code or Gray code to binary, we use X-OR gates. How???

Four-bit binary-to-Gray conversion logic Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Four-bit Gray-to-binary conversion logic Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Multiplexers & Demultiplexers MUX & DEMUX

Mutiplexer (MUX) A circuit that selects binary information from one of many input lines, and directs the information to a single output line. The selection of a particular input line is controlled by a set of input variables, called “selection inputs”. Normally, there are 2n input lines and n selection inputs. Output lines = ?

2-to-1 Multiplexer Data selector A 2 input multiplexer Data selector SELECT input code determines which input is transmitted to output Z.

4-to-1 Multiplexer Write the output equation for Z Verify the circuit A 4 input multiplexer Write the output equation for Z Verify the circuit above

8-to-1 Multiplexer 16-to-1 MUX: 74150 Larger multiplexers can be constructed from smaller ones. An 8-to-1 multiplexer can be constructed by cascading smaller multiplexers as shown: 16-to-1 MUX: 74150

“Smart” Design Exercise Design a 16:1 MUX by cascading 4:1 MUXes

Multiplexer Application Example: 74157- consists of four separate 2-input multiplexers.

Demutiplexer (DeMUX) Opposite function of the multiplexer. Information received from a single line is transmitted to one of 2n possible output lines. The output line chosen is controlled by the n selection inputs. Black box view?

Demultiplexer 1-line-to-8-line multiplexer Data input is transmitted to only one of the outputs as determined by the select input code.

1-to-2 DeMUX D 1 Y1 Y0 Select Black box view Output equations D 1 Y1 Y0 Select Black box view Output equations Logic circuit

1-to-4 DeMUX

Mux-Demux Application: Example This enables sharing a single communication line among a number of devices. At any time, only one source and one destination can use the communication line.

Multiplexer & Demultiplexer - A Second Look -

3-7 Multiplexers (Pemultipleks) Selects binary information from one of many input lines and directs the information to a single output line. The selection of an input line is controlled by a set of variables, i.e. the “selection” inputs. Also called “Data Selector”.

Mutiplexer (MUX)

4-to-1-Line Multiplexer

8-to-1-Line Multiplexer

16-to-1-Line Multiplexer

… Multiplexer Also called “MUX”. Resembles a decoder circuit. 2n input lines. n selection inputs (SEL0, …, SELn). Can be constructed from: Decoders. Transmission gates.

… Multiplexer May have an Enable, EN, input, to control its operation. EN = Inactive  Outputs Disabled. EN = Active  Normal Operation. EN is useful when using 2 or more MUXes to obtain a bigger MUX (i.e. more inputs). Combine MUXes in parallel with the same SEL and EN lines.

Quadruple 2-to-1-Line Multiplexer…

…Quadruple 2-to-1-Line Multiplexer Has ____ number of MUXes. YO can be selected from either A0 or B0. Y1- from either A1 or B1, etc. EN=1, S=0, all A inputs are passsed to the outputs. S=1, all B inputs are passed to the outputs. EN=0, all outputs are 0.

Implementing a Boolean Function with a Multiplexer … A multiplexer is basically a decoder that includes the OR gate within the block. To implement a Boolean function of n variables with a mux having n selection inputs and 2n data inputs, one for each minterm. The minterms are generated in a mux by the circuit associated with the selection inputs. Individual minterms can be selected by the data inputs.

… Implementing a Boolean Function with a Multiplexer A more efficient way To implement a Boolean function of n variables with a mux having only n-1 selection inputs and 2n-1 data inputs. Example 1: F (X,Y,Z) = m (1, 2, 6, 7)

Example 1

… Implementing a Boolean Function with a Multiplexer General procedure: Produce Truth Table for Boolean function. The first n-1 variables are applied to the selection inputs of the mux. The remaining single variable of the function is used for the data input.

… Implementing a Boolean Function with a Multiplexer For each combination of the selection variables, we evaluate the output as a function of the last variable, i.e. a 0, 1, the variable or its complement. These values are then applied to the data inputs in the proper order.

Example 2: Implementing a 4-Input Function with a Multiplexer F (A, B, C, D) = m (1, 3, 4, 11, 12, 13, 14, 15) Implement the function with a mux having 3- selection inputs.

… Example 2

Demultiplexer Performs the inverse function of a multiplexer. Receives information from a single line and transmits it to one of possible 2n possible output lines. The selection is is controlled by the bit combination of n selection lines. A demultiplexer is identical to a 2-to-4-line decoder with enable input. A decoder with enable input = A Decoder/Demultiplexer.

1-to-4-Line Demultiplexer

Design Preparation for Lab 4 4:1 MUX 1:5 DeMUX Truth Table K-maps & minimized equations Circuit diagram Extra Exercise A 16:1 MUX using cascaded 4:1 MUXes

Functions of Combinational Logic Adder Encoder Comparator Decoder Multiplexer Demultiplexer Parity Generator Parity Checker Code Converters

Error Detection & Correction Codes PARITY METHOD: Even Parity Odd Parity

Parity Bit Is an extra bit included with the data bits. To detect errors in data communication & processing.

Error-Detection Codes Redundancy (e.g. extra information), in the form of extra bits, can be incorporated into binary code words to detect and correct errors. A simple form of redundancy is parity, an extra bit appended onto the code word to make the number of 1’s odd or even. Parity can detect all single-bit errors and some multiple-bit errors. A code word has even parity if the number of 1’s in the code word is even. A code word has odd parity if the number of 1’s in the code word is odd.

4-Bit Parity Code Example Fill in the even and odd parity bits: The codeword "1111" has even parity and the codeword "1110" has odd parity. Both can be used to represent 3-bit data. Even Parity Odd Parity Message Parity Message Parity - - 000 000 - - 001 001 - - 010 010 - - 011 011 - - 100 100 - - 101 101 - - 110 110 - - Even Parity Bits: 0, 1, 1, 0, 1, 0, 0, 1 Odd Parity Bits: 1, 0, 0, 1, 0, 1, 1, 0 111 111 - - 168

Parity Generator & Parity Checker Odd Parity Even Parity

Error-Detection A parity bit is a scheme for detecting errors during transmission of binary info. A parity bit is an extra bit included with the binary message to make the number of 1’s either odd or even. The message, including the parity bit, is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond to the one transmitted.

Error-Detection The circuit that generates the parity bit in the transmitter is a parity generator. The circuit that checks the parity bit in the receiver is a parity checker.

Error-Detection Parity generator truth table *For odd parity, the bit P is generated so as to make the number of 1’s odd (including P) X Y Z P 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 Odd Parity Generator

* The three-bit message (X, Y, Z) and parity bit (P) are transmitted to their destination, where they are applied to a parity checker circuit. An error occurs during transmission if the parity of the four bits is even, since the binary info transmitted was originally odd. The output C of the parity checker should be a 1 when an error occurs, i.e. when the number of 1’s in the four inputs is even. X Y Z P C 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Odd Parity Checker

Parity is used in digital circuits to check for errors in transmission. In Four bit transmission a parity bit is added to make the fifth bit. In a eight bit transmission a parity bit is added to made a ninth bit. And so on.

ODD Parity In ODD parity when we add the bits together disregarding weight we get or want to get an odd number. 0000 is a four bit message add a parity bit to make it odd 10000 Odd parity is satisfied 00011001 is an eight bit message add a parity bit to make it odd 000011001 Odd parity is satisfied Parity bit

EVEN parity In EVEN parity when we add the bits together disregarding weight we get or want to get an even number. 0000 is a four bit message add a parity bit to make it even 00000 Even parity is satisfied 00011001 is an eight bit message add a parity bit to make it even 100011001 Even parity is satisfied Parity bit

How to generate a parity bit Use exclusive ORs and Exclusive NORs

How to make a parity checker

Odd or even parity ~ 0 out of a parity checker means the parity checks and all is ok ~ 1 out of a parity checker means there is an error

Parity Generator/Checker - A Second Look -

Tip to generate/check “parity” “The sum (disregarding carries) of an even number of 1’s is always 0, and the sum of an odd number of 1’s is always 1.”  To determine if a given code has even or odd parity, all the bits in the code must be summed. Summation can be done using Ex-OR gate

Parity Checker Circuit When the no. of inputs is even  Output, X, is 0 When the no. of inputs is odd  Output, X, is 1

The 9-bit parity generator/checker. Input is 8-bits of data and 1 parity bit When there is an even no. of 1’s at the inputs, the Σ Even is high while the Σ Odd is low.

Parity Checker Function When used as an EVEN Parity Checker, If a parity error occurs, the Σ Even is low while the Σ Odd is high. When used as an ODD Parity Checker, If a parity error occurs, the Σ Odd is low while the Σ Even is high.

Parity Generator Function When used as an EVEN Parity Generator, The parity bit is taken at the Σ Odd output. It is 0 if there is an even no. of 1’s, and is 1 if there is an odd no. When used as an ODD Parity Generator, The parity bit is taken at the Σ Even output. It is 0 if there is an odd no. of 1’s, and is 1 if there is an even no.

Design Exercise Derive the gate-level schematic circuit for the 9-bit Parity Generator/Checker explained above.

Extra Design Exercise - Decoder The 4-line-to-16-line Decoder (Active low outputs) The BCD to Decimal Decoder The BCD to 7-segment Decoder

Extra Design Exercise - Encoder 16-line-to-4-line Encoder using the 8-line-to- 3-line encoder in cascade The Decimal to BCD Encoder The Keypad Encoder, as in the next slide

Keypad Encoder The keypad consists of the keys 0 to 10. When one of the keys is pressed, the decimal digit is encoded to the corresponding BCD code. When a key is depressed, the line is connected to ground, i.e. low input. The “0” key is not connected as the BCD output is 0 when none of the other keys is depressed.

Design Exercise Use truth table and K-map to design: A 2-to-1 MUX A 1-to-2 DeMUX

Extra Design Exercise – MUX and DeMUX Using the circuits from the previous slide, design by using the cascade/array/”smart design” technique: A 4:1 MUX using 2:1 MUXes A 8:1 MUX using 4:1 MUXes A 16:1 MUX using 8:1 MUXes

A 1:4 DeMUX using 1:2 DeMUX A 1:8 DeMUX using 1:4 DeMUX A 1:16 DeMUX using 1:8 DeMUX