Scheduling Issues on a Heterogeneous Single ISA Multicore IRISA, France Robert Guziolowski, André Seznec. Contact: 1. M. Becchi and P. Crowley. Dynamic thread assignment on heterogeneous multiprocessor architectures. Proceedings of the 3rd conference on Computing frontiers, pages 29–40, T. Sherwood, S. Sair, and B. Calder. Phase tracking and prediction. Proceedings of the 30 th Annual International Symposium on Computer Architecture, IEEE CS Press, pages 336–349, S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 111–122, SESC, References This work was partially supported by an Intel research grant, an Intel research equipment and by the European Commission in the context of SARC integrated project. We investigate the following conditions as implemented as different exchangers: Scheduling processes on a heterogeneous multicore processor is a much more complicated task, as the differences in the cores can appear in: number of Functional Units, L1 data and instruction caches, hierarchy of the lower level caches, issue width, and many more. Thus, a simple round-robin scheduling may not be sufficient. Additional dynamic mechanisms have to be used in order to better utilize all the available cores. Our objective is to investigate possible scheduling mechanisms for single ISA heterogeneous multicore. CPU core A core B RR P1P1 P2P2 PnPn … ? Future We plan to investigate other exchangers (presented above) as well as use a mix of exchangers between the core classes. We also want to introduce SMT cores into our research. Moreover, to have more clear view of the shared caches effects, we plan to intro- duce fair cache sharing and partitioning into our simulations, as proposed in [3]. We plan to investigate scheduling issues with the use of parallel workloads. Results Testbed Exchangers ExchangerCompared values IPCValues of IPC of the processes [1] IPC%Percent usage of the theoretically achievable IPC of the core (exploiting phase-behavior [2]) ONEILRatios of the oldest not-executed instructions of type load which cause the core to stall (on-going work) othersBranch predictor characteristics, utilization of FUs in SMT cores, composition of above parameters, etc. Scheduling processes on a single core or homogeneous multicore processors is a relatively easy task, using for instance a round-robin (RR) algorithm. CPU core RR P1P1 P2P2 PnPn … CPU core RR P1P1 P2P2 PnPn … Known issues and objective Processes are scheduled on the available cores using a global round-robin scheduler with the period schedule_period. By exchanger we define the mechanisms which migrates the processes between the core classes when specific conditions are met. Exchangers check the conditions and migrate selected processes between the core classes with the period exchange_period. Of course, exchange_period < schedule_period. Proposed mechanism is based on [1], but it allows investigating architectures with higher heterogeneity more easily. Proposed mechanism We define a core class as a non- empty set of the cores having the same characteristics. RR P1P1 P2P2 PnPn … CPU … core A CoreClass0 core N CoreClassN core B CoreClass1 Exchanger0Exchanger1 ExchangerN All simulations are conducted with the use of SESC simulator [4] and SPEC2000 benchmarks. 3 types of cores (A, B, and C) with different characteristics gathered into 3 core classes (depending on the configuration). L3 cache AA L2 cache AA L3 cache AA L2 cache BBBB L3 cache AA L2 cache BB CCCC L3 cache A L2 cache CCCC BBBB 4 test configuration of cores 4A 1A4B4C 2A2B4C 2A4B