Front-End Electronics for G-APDs Stefan Ritt Paul Scherrer Institute, Switzerland

Stefan Ritt, PSIG-APD Workshop, GSI, Traditional Front-End Electronics Time is measured with Discriminator/TDC Energy is measured with gated charge-ADC TDC Amplifier Shaper DiscriminatorMeasure Time Moving average baseline hits G-APD ADC Measure Amplitude/Charge What about pile-up?

Stefan Ritt, PSIG-APD Workshop, GSI, Flash ADC Technique 60 MHz 12 bit Preamplifier G-APD Shaper Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping would be unnecessary if FADC would be fast enough Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping would be unnecessary if FADC would be fast enough FADC 5 GHz 12 bit Transimpedance Preamplifier G-APD FADC

Stefan Ritt, PSIG-APD Workshop, GSI, How to measure best timing? Simulation of MCP with realistic noise and different discriminators J.-F. Genat et al., arXiv: (2008)

Stefan Ritt, PSIG-APD Workshop, GSI, Switched Capacitor Array Principle Shift Register Clock IN Out “Time stretcher” GHz  MHz Waveform stored Inverter “Domino” ring chain ns FADC 33 MHz Keep Domino wave running in a circular fashion and stop by trigger  Domino Ring Sampler (DRS)

Stefan Ritt, PSIG-APD Workshop, GSI, Switched Capacitor Array Cons No continuous acquisition Calibration for precise timing External (commercial) FADC needed Pros High speed (~5 GHz) high resolution (~12 bit equiv.) High channel density (8 channels on 5x5 mm 2 ) Low power (30 mW / channel) Low cost (~ 10 € / channel chip only) tt tt tt tt tt

Stefan Ritt, PSIG-APD Workshop, GSI, DRS4 Chip Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm 2, radiation hard 8+1 ch. each 1024 cells Differential inputs, differential outputs Sampling speed 1 GSPS … 6 GSPS, PLL stabilized Readout speed 30 MHz, multiplexed or in parallel

Stefan Ritt, PSIG-APD Workshop, GSI, ~12 bit resolution at 5 GSPS 11.5 bits effective resolution <8 bits effective resolution

Stefan Ritt, PSIG-APD Workshop, GSI, Random Jitter Results Sine curve frequency fitted for each measurement (PLL jitter compensation (~25ps) ) Encouraging result for DRS3: 2.7 ps RMS (best channel) 3.9 ps RMS (worst channel) phase error in fitting sine wave Differential measurement t1 – t2 adds a  2, needs to be verified by measurement Measurement of n points on a rising edge of a signal improves by  n Sine curve frequency fitted for each measurement (PLL jitter compensation (~25ps) ) Encouraging result for DRS3: 2.7 ps RMS (best channel) 3.9 ps RMS (worst channel) phase error in fitting sine wave Differential measurement t1 – t2 adds a  2, needs to be verified by measurement Measurement of n points on a rising edge of a signal improves by  n Measurements for DRS4 currently going on, expected to be slightly better

Stefan Ritt, PSIG-APD Workshop, GSI, Simultaneous Write/Read Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0 FPGA Channel 0Channel 1 1 Channel 0 readout 8-fold analog multi-event buffer Channel 2 1 Channel 1 0 Expected additional crosstalk ~few mV

Stefan Ritt, PSIG-APD Workshop, GSI, Comparison with other chips MATACQ D. Breton LABRADOR G. Varner DRS4 S. Ritt Bandwidth (-3db) 300 MHz> 1000 MHz950 MHz Sampling frequency 1 or 2 GHz10 MHz … 3.5 GHz1 GHz … 5 GHz Full scale range ±0.5 V+0.4 …2.1 V±0.5 V Effective #bits 12 bit10 bit12 bit Sample points 1 x x 2568 x 1024 Channel per board 4N/A32 Digitization 5 MHzN/A30 MHz Readout dead time 650  s150  s3  s – 370  s Integral nonlinearity ± 0.1 % ± 0.05% Radiation hard No Yes (chip) Commercial Board V1729 (CAEN)-planned (CAEN)

Stefan Ritt, PSIG-APD Workshop, GSI, DRS Boards 32 channels input General purpose VPC board built at PSI USB evaluation board

Stefan Ritt, PSIG-APD Workshop, GSI, Experiments using DRS chip MAGIC-II 400 channels DRS2 MEG 3000 channels DRS2 BPM for 1000 channels DRS4 (planned) MACE (India) 400 channels DRS4 (planned)

Waveform Analysis What can we learn from acquired waveforms?

Stefan Ritt, PSIG-APD Workshop, GSI, On-line waveform display click template fit pedestal histo  848 PMTs “virtual oscilloscope”

Stefan Ritt, PSIG-APD Workshop, GSI, QT Algorithm original waveform smoothed and differentiated (Difference Of Samples) Threshold in DOS Region for pedestal evaluation integration area t Inspired by H1 Fast Track Trigger (A. Schnöning, Desy & ETH) Difference of Samples (= 1 st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  100ps resolution for 1ns sampling time Inspired by H1 Fast Track Trigger (A. Schnöning, Desy & ETH) Difference of Samples (= 1 st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  100ps resolution for 1ns sampling time Can be implemented in FPGA

Stefan Ritt, PSIG-APD Workshop, GSI, Pulse shape discrimination   Leading edge Decay time AC-coupling Reflections Example:  /  source in liquid xenon detector (or:  /p in air shower)

Stefan Ritt, PSIG-APD Workshop, GSI,  -distribution     = 21 ns   = 34 ns Waveforms can be clearly distinguished   = 21 ns   = 34 ns Waveforms can be clearly distinguished

Stefan Ritt, PSIG-APD Workshop, GSI, Coherent noise  i V i (t) All PMTs Pedestal average Charge integration Found some coherent low frequency (~MHz) noise Energy resolution dramatically improved by properly subtracting the sinusoidal background Usage of “dead” channels for baseline estimation Found some coherent low frequency (~MHz) noise Energy resolution dramatically improved by properly subtracting the sinusoidal background Usage of “dead” channels for baseline estimation Important in low signal applications such as RICH

Stefan Ritt, PSIG-APD Workshop, GSI, Pileup recognition original derivative  t = 15ns E1E2  T 8ns  T 10ns  T 15ns  T 50ns  T 100ns MC simulation Rule of thumb: Pileup can be detected if  T ~ rise-time of signals

Stefan Ritt, PSIG-APD Workshop, GSI, Template Fit Determine “standard” PMT pulse by averaging over many events  “Template” Find hit in waveform Shift (“TDC”) and scale (“ADC”) template to hit Minimize  2 Compare fit with waveform Repeat if above threshold Store ADC & TDC values  Experiment 500 MHz sampling

Stefan Ritt, PSIG-APD Workshop, GSI, Conclusions Switched Capacitor Array techniques has prospects to trigger a quantum step in data acquisition for G-APDs The DRS chip has been designed with maximum flexibility and can therefore be used in many applications Collaboration on a scientific basis is very welcome, chips and evaluation board available from PSI on a non-profit basis Datasheets, publications:

Stefan Ritt, PSIG-APD Workshop, GSI,

Backup Slides

Stefan Ritt, PSIG-APD Workshop, GSI, Bandwidth Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) final bus width Simulation 850 MHz (-3dB) QFP package Measurement

Stefan Ritt, PSIG-APD Workshop, GSI, ROI readout mode readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz e.g MHz  3 us dead time (2.5 ns / 12 channels)

Stefan Ritt, PSIG-APD Workshop, GSI, Daisy-chaining of channels Channel 0 – 1024 cells Channel 1 – 1024 cells Channel 2 – 1024 cells Channel 3 – 1024 cells Channel 4 – 1024 cells Channel 5 – 1024 cells Channel 6 – 1024 cells Channel 7 – 1024 cells Domino Wave Generation DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells

Stefan Ritt, PSIG-APD Workshop, GSI, Interleaved sampling delays (200ps/8 = 25ps) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) 5 GSPS * 8 = 40 GSPS

Stefan Ritt, PSIG-APD Workshop, GSI, Trigger an DAQ on same board Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GHz samples) though same 8-channel FADCs analog front end DRS FADC 12 bit 65 MHz MUX FPGA trigger LVDS SRAM DRS4 global trigger bus “Free” local trigger capability without additional hardware

Stefan Ritt, PSIG-APD Workshop, GSI, Datasheet