ASIC Activities for the PANDA GSI Peter Wieczorek

2 Overview Existing ASIC and Improvement Setup for Crystal Matrix Measurements Data Acquisition

Peter Wieczorek 3 Existing ASIC and Improvement

Peter Wieczorek 4 Block Schematic - preamplifier first shaper second shaper third shaper

Peter Wieczorek 5 ASIC Layout Shaper stage Output stage Preamplifier stage Channel 1 Channel 2 Voltage reference Prozess: 350 nm - CMOS Dimension: 3.3 mm x 3.3 mm Connections: 64 Components: Transistors: 4841 Capacitors: 1729 Resistors: 386

Peter Wieczorek 6 Results Requirements T = - 20° C Unit Noise: ± 35e-e- Max. input charge:77,84 ± 0,4 pC Dyn. range: ± 2511 Integration time: ± 3ns Event rate:350500kHz Power consumption:6052 ± 1mW/Channel

Peter Wieczorek 7 Next ASIC Iteration Next iteration should be the final design Implementation of an additional DAC Extention of the existing logic Define # of bits for chip ID Optimisation of the power consumption Open questions: What is the next readout device after the ASIC ? (Power consumption, output load, …) How many ASICs will be connected to a cluster ? (Chip ID)

Peter Wieczorek 8 Setup for Crystal Matrix Measurements

Peter Wieczorek 9 Readout Chain Crystal APD ASIC Differential output signal

Peter Wieczorek 10 Setup Matrix readout 4 x 4 array One APD per crystal Seperate high voltages Two APDs connected one ASIC 4 x 4 matrix 2 ASICs on one PCB 1 16

Peter Wieczorek 11 Crystal Matrix Status: Mechanical setup:Gießen/GSIavailable Crystals:Gießenavailable ASICs:GSIavailable PCB with buffer:GSIUnder development APDs:Gießenavailable Cooling system:Gießenavailable Differential ADC:KVI ?? DAQ system:KVI ??

Peter Wieczorek 12 Data Acquisition

Peter Wieczorek 13 DAQ - System Crystal APD ASIC DAQ - System Digitize the analog output signals

Peter Wieczorek 14 Readout Board Developed by J.Hoffmann Connection to the Data Acquisition LAB: USB - Connection 16 Differential analog inputs Input range: ± 1 V ADC: 12 Bit, 65MS/s

Peter Wieczorek 15 Thanks….