A Readout System Utilizing the APV25 ASIC for the Forward GEM Tracker in STAR G. J. Visser 1, J. T. Anderson 2, B. Buck 3, A. S. Kreps 2, T. Ljubicic 4 1 Indiana University Center for Exploration of Energy and Matter, USA 2 Argonne National Laboratory, USA 3 Massachusetts Instituteof Technology, USA 4 Brookhaven National Laboratory, USA Introduction The Forward GEM Tracker (to be online for FY12 run) will extend STAR’s tracking reach to η =2, covering the Endcap EMC, with the principal focus being e + /e − discrimination for the W program. The FGT is comprised of six triple GEM chambers with pad/strip readout planes, and utilizes the APV25-S1 frontend ASIC developed for the CMS silicon tracker. The GlueX detector system, now under construction for Jefferson Lab Hall D includes the 3098 channel straw tube central drift chamber (CDC) surrounding the target, and the 24 layer planar cathode strip forward drift chamber (FDC) in the forward region. The FDC has 2304 anode wires with discriminator/TDC readout and cathode strips. An 8 channel frontend ASIC has been developed for these detectors in TSMC 0.25 µm CMOS technology. † The CDC and the cathode strips of the FDC, a total of channels, require 12 bit ADC (waveform digitizer) readout capable of deadtimeless operation at up to 200 kHz trigger rate, blahblah This work was supported in part by the Offices of NP and HEP within the U.S. DOE Office of Science and by the U.S. NSF. Design choices Some compromises are necessary for maximum channel density. The analog signal path must be kept relatively simple. In particular: A passive shaper uses no power, little board area An ADC driver stage is not necessary if we can keep the drive impedance reasonably low without it Differential drive is not necessary if the ADC uses a (relatively) high VDD and if we can tolerate a little nonlinearity However we do not compromise on the line receiver, this is the most crucial element. It is important to: Receive differential signal accurately Not inject common-mode ground noise back to cable & front end electronics Equalize cable frequency response Receiver / freq eq. Shaper ADC σ = 5.62 (12-bit: 1.40) 11.5 ENOB Open input: Typical FDC event (preliminary data from FDC prototype) 15 MHz* sine input, single event 100 pt readout 21 hostile (red) and 1 hostile (blue & brown) Indicates ~2% crosstalk in neighbor channels, acceptable but will try to reduce with layout improvements DAC per channel σ = 0.43σ = 0.52 Noise and linearity are evaluated with open input and with 14.9 MHz sine input. Nonlinearity ≈ 0.05 % ADCFEFIFO ADCFEFIFO … (36 ch total) … ADCFEFIFO ADCFEFIFO ADCFEFIFO ADCFEFIFO ADCFEFIFO … (36 ch total) … ADCFEFIFO ADCFEFIFO ADCFEFIFO Mezzanine board Main board Processor FPGA Output FIFOVME slave 2eSST etc. Each 160 MB/s i.e kHz 160 MB/s 1 MB 320 MB/s FE (Front-end processing): This includes acquisition buffer writing, point extraction, lookahead zero suppression, channel number & header insertion Channel data FIFO: 1024 words (16 bits + 2 flags, internal use only) XC3SD3400A-4 Frontend FPGA XC3S500E-4 12 total, 6 ch each The bottom line… Noise and nonlinearity Features 72 channels in a 6U VME64x/VXS module, $55 per channel Assembly option for 12 or 14 bits Up to 125 MSPS, internal or external sample clock Differential input 440 mV full scale Cable loss equalization Shaper/anti-alias filter 24 ns peaking Independent offset DAC per channel Preamp test pulser output Acquisition buffer: Dual-port circular buffer, 2048 points (19.5 μ s) FPGA-based signal processing 1 MB buffer and 2eSST readout Remote firmware upload (VME) opto-isolated I 2 C master (2×) cable to FEE Complete integrated readout and power system for FGT Current status 3 modules assembled & tested Interim firmware (FE deadtime, no block transfers) Deployed in support of CDC and FDC development Next steps: Full deadtimeless readout, 2eSST transfers Minor changed to layout (obsolence, crosstalk) Develop production test Pre-production run (20 modules) in early modules (+spares) in 2012 ADC (quad) frontend FPGA Crosstalk Single event 1000 pt readout *Corresponds to peaking time ≈33 ns for combined system (preamp, cable, ADC) Readout module for 2×12 APV (3072 det. channels) The PCB is 10 layers w/ 6 planes (3 GND), 0.003” buried capacitance. † GAS II: A Versatile Wire Chamber Readout ASIC. N. Dressnandt, N. Doshi, M. Newcomer., IEEE NSS System response Preamp + 18 m cable + ADC main FPGA analog line receiver / filter THERE ARE MANY ELEMENTS OF OLD POSTER HERE STILL TO BE CHANGED/DELETED!! to readout / control backplane (CPCI style) FEE Power Supply ±1.8V 2.5A remote reg. 0 – 360° clock phase shifter (4×) for APV & ADC