Course: High-Speed and Low- Power VLSI (97.575) Professor: Maitham Shams Presentation: Presentation: True Single- Phase Adiabatic Circuitry By Ehssan.

Slides:

Advertisements

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Advertisements

Feb. 17, 2011 Midterm overview Real life examples of built chips

A Resonant Clock Generator for Single-Phase Adiabatic Systems Conrad H. Ziesler Marios C. Papaefthymiou University of Michigan, Ann Arbor, MI Suhwan Kim.

Pass Transistor Logic. Agenda  Introduction  VLSI Design methodologies  Review of MOS Transistor Theory  Inverter – Nucleus of Digital Integrated.

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: basic construction.

Power Reduction Techniques For Microprocessor Systems

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

Introduction to Digital Systems By Dr. John Abraham UT-Panam.

Digital Integrated Circuits© Prentice Hall 1995 Devices The MOS Transistor.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of.

Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.

 C. H. Ziesler etal., 2003 Energy Recovering ASIC Design Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science.

10/27/05ELEC / Lecture 161 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Design, Verification, and Test of True Single-Phase Adiabatic Multiplier Suhwan Kim IBM Research Division T. J. Watson Research Center, Yorktown Heights.

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

1 Clockless Logic Montek Singh Tue, Mar 16, 2004.

8/19/04ELEC / ELEC / Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Fall 2004 Vishwani.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 12 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power.

8/18/05ELEC / Lecture 11 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Introduction to VLSI Circuits and Systems, NCUT 2007 Chapter 12 Arithmetic Circuits in CMOS VLSI Introduction to VLSI Circuits and Systems 積體電路概論賴秉樑 Dept.

 C. H. Ziesler et al., 2003 Energy Recovering Computers 1 Advanced Computer Architecture Laboratory University of Michigan Conrad H. Ziesler 1 Joohee.

Towards An Efficient Low Frequency Energy Recovery Dynamic Logic Sujay Phadke Advanced Computer Architecture Lab Department of Electrical Engineering and.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

10/20/05ELEC / Lecture 141 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

 C. H. Ziesler et al., 2003 Energy Recovery Design for Low-Power ASICs Conrad H. Ziesler 1 Joohee Kim 1 Suhwan Kim 2 Marios C. Papaefthymiou 1 1 Advanced.

Fall 2006: Dec. 5 ELEC / Lecture 13 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani.

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 11 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal.

Low Power Design and Adiabatic Circuits P.Ranjith M.Tech(ICT)

Digital Integrated Circuits for Communication

Low power CDN. SPEED Operate vdd at half rails Data should operate at full rails.

Types of Operational Amplifiers

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.

04/26/05 Anthony Singh, Carleton University, MCML - Fixed Point - Integer Divider Presentation #2 High-Speed Low Power VLSI – Prof. Shams By Anthony.

A Presentation on. Cascadable Adiabatic Logic Circuits

© Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits Jan M. Rabaey.

Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.

Low-Power CMOS Logic Circuit Topic Review 1 Part I: Overview (Shaw) Part II: (Vincent) Low-Power Design Through Voltage Scaling Estimation and Optimization.

Evolution in Complexity Evolution in Transistor Count.

1 IN THE NAME GOD Advanced VLSI Class Presentation A 1.1GHz Charge Recovery Logic Insructor : Dr. Fakhrayi Presented by : Mahdiyeh Mehran.

Mehdi Sadi, Italo Armenti Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication.

A Class Presentation for VLSI Course by : Fatemeh Refan Based on the work Leakage Power Analysis and Comparison of Deep Submicron Logic Gates Geoff Merrett.

THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area l Performance »Speed (delay) »Power Consumption »Energy.

Logic Synthesis for Low Power(CHAPTER 6) 6.1 Introduction 6.2 Power Estimation Techniques 6.3 Power Minimization Techniques 6.4 Summary.

1 Power Dissipation in CMOS Two Components contribute to the power dissipation: »Static Power Dissipation –Leakage current –Sub-threshold current »Dynamic.

Adiabatic Logic Circuit for Biomedical Applications Prepared by: Muhammad Arsalan Presented to: Dr. Maitham Shams.

Ratioed Circuits Ratioed circuits use weak pull-up and stronger pull-down networks. The input capacitance is reduced and hence logical effort. Correct.

Washington State University

DCSL & LVDCSL: A High Fan-in, High Performance Differential Current Switch Logic Families Dinesh Somasekhaar, Kaushik Roy Presented by Hazem Awad.

Adiabatic Logic as Low-Power Design Technique Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams Mar. 02, 2005.

Low Power – High Speed MCML Circuits (II)

L 19: Low Power Circuit Optimization. Power Optimization Modeling and Technology Circuit Design Level –logic Families –low-power Flip-Flops –low-power.

Lecture 10: Circuit Families. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 10: Circuit Families2 Outline  Pseudo-nMOS Logic  Dynamic Logic  Pass Transistor.

1 A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, and Tsai-Wen.

Pass Transistor Logic EMT 251. Pass Transistor Logic I n p u t s Switch Network Out A B B B.

Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder Babu, H. M. H. Chowdhury, A.R, “Design of a reversible binary.

EE141 © Digital Integrated Circuits 2nd Inverter 1 Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje.

Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder.

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: basic construction.

Adiabatic Circuits Mohammad Sharifkhani. Introduction Applying slow input slopes reduces E below CV2 Useful for driving large capacitors (Buffers) Power.

Copyright Agrawal, 2007ELEC6270 Spring 13, Lecture 101 ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal.

Seok-jae, Lee VLSI Signal Processing Lab. Korea University

ELEC Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Design Technologies.

Adiabatic Technique for Energy Efficient Logic Circuits Design

IV UNIT : GATE LEVEL DESIGN

Vishwani D. Agrawal James J. Danaher Professor

Vishwani D. Agrawal James J. Danaher Professor

Presentation transcript:

Course: High-Speed and Low- Power VLSI (97.575) Professor: Maitham Shams Presentation: Presentation: True Single- Phase Adiabatic Circuitry By Ehssan Hosseinzadeh Special Student

Outline Introduction Adiabatic – Switching Circuits True Single-Phase adiabatic Circuit Results Conclusion References

Introduction Importance of Reducing Power Dissipation Techniques =>Parallelism => Pipeline => Transformation => Reduce the Chip wide Supply voltage => Energy Recovery

Conventional Energetic Swinging voltage on capacitor: - Zero => V -V => Zero Engergy dissipation per transition E= ½ CV 2 Adiabatic - Switching Circuits

Recovery Energy Adiabatic - Switching Circuits E diss = P. T = I 2. R.T = (RC/T) CV 2

True Single-Phase adiabatic Circuit Different Approaches: Signal voltage swing > Vt of CMOS => Adiabatic Amplification Dynamic logic families => 2N2P, 2N-2N2P, => True Signle-Phase Energy-Recovery Logic (TSEL) => Source–Coupled Adiabatic Logic (SCAL)

True Single-Phase Energy-Recovery Logic (TSEL) Cascades are composed of alternating PMOS and NMOS gates TSEL GATES True Single-Phase adiabatic Circuit

PMOS DP: Vpc: H-L Vpc  VRP - |vtp| EP: Vin: H, Vpc:L Vpc < VRP - |vtp| Ddp > |Vtp| Vpc  VRP - |vtp| NMOS EN: Vpc > VRN + |vtn| CN: Vpc  VRN + |vtn|

TSEL Cascades TSEL Cascades are built by stringing together alternating PMOS and NMOS gates

SCAL Gates Single Phase power Clock Operation Tunable Current Source at each Gate

Vpc Vbp Vbn DP: Vpc: H-L Adiabatlically till Vpc > |Vtp| EP: Vpc: L-H Vbp increase Vdd - |Vbp| > |Vtp| Vpc < Vxp - |Vtp| Dpp > |Vtp| Vpc > Vxp - |Vtp|

SCAL Cascades

Results 8-bit Carry-Lookahead adder (CLAs) Developed in Static CMOS, PAL, 2N2P, TSEL, SCAL (0.5um) Freq: 10 –200 MHz SCAL CLA => 1.5 – 2.5 times more efficient than PAL, 2N2P SCAL CLA => 2 – 5 times less dissipative than purely combinational or pipelined CMOS

Conclusion True Single-phase adiabatic logic family: TSEL, SCAL Source-coupled variant of TSEL => Increase energy efficiency by using tunable current source Avoid the problems: Multiple Power-clock schemes - Increased energy dissipation - Layout Complexity in clock distribution, - Clock Skew - Multiple power–clock generator

References True Single Phase Adiabatic Circuitry, Suhwan Kim and Mario Papaefthymiou Energy Recovery For Low Power CMOS, WC Athas and N. Tzartanis Low Power Digital Systems Based on Adiabatic-Switching Principles, William C. Athas