Advanced Hardware/Software Optimization Techniques for Application Specific MCSoC m Yumiko Kimezawa Supervised by Prof. Ben Abderazek Adapted Systems Laboratory August 22, 2011Master's Thesis Research Plan1

Outline 1.Background 2.Problems 3.Research goal 4.Proposal 5.Conclusion 6.Schedule August 22, 2011Master's Thesis Research Plan2

Background Electrocardiography (ECG) -Electrical activity of the heart -Used for diagnosis of heart disease Processing ECG signals involves heavy computation Previous proposed ECG processing system -Parallel processing using additional cores for analyzing ECG signals August 22, 2011Master's Thesis Research Plan3

System architecture 3-lead system is implemented -The total logic utilization is about 3 times as large as one of single-lead system - The total processing time is about 50 % from the single lead system ADC 1 ADC 12 FIR 1 FIR 12 Buffer ECG Signal Analysis 1:Signal reading 2:Filtering3:Analysis4:Display 12 leads External Memory Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms Not implemented Our ideal system architecture August 22, 20114Master's Thesis Research Plan

System architecture (2) The system consists of mainly 2 modules Master module -Signal reading, filtering and display part PPD module -Analyzing ECG signal using Period-Peaks Detection (PPD) algorithm August 22, 20115Master's Thesis Research Plan

Problems No A/D converter -Can not get actual data -Can not estimate real system complexity and power -Difficultly estimation of real processing time Can not use hardware effectively -The more leads, the more larger logic utilization Current software is not effective -ECG signals are processed one by one August 22, 20116Master's Thesis Research Plan

Research goal Analyzing actual data from sensors Proposal of the system using hardware effectively Analyzing 12-lead ECG signals in parallel August 22, 20117Master's Thesis Research Plan

Proposal Hardware/Software optimization -Hardware Adding A/D converters Fast data transfer between each memory DMA controller -Software Putting together a block of some ECG signals and processing the signals every blocks Parallelizing software August 22, 2011Master's Thesis Research Plan8

Proposal architecture : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory FPGA Analog ECG data from the sensor Line-in Data conversion HSMC A/D converter DMA controller August 22, 20119Master's Thesis Research Plan

Conclusion Previous proposed system can not get actual data Software of the system is not effective The system needs HW/SW optimization -Adding A/D converters -Parallelization of software August 22, Master's Thesis Research Plan

Schedule September - October, Investigating suitable resolution and sampling rate for A/D conversion -Selecting appropriate an A/D converter November, March, Adding the A/D converter into the system -Getting actual data using the sensor August 22, Master's Thesis Research Plan

Schedule (2) April - June, Adding DMA controller into the system July - August, Optimization of software September - December, Debugging the system November, Beginning to start writing master’s thesis August 22, Master's Thesis Research Plan

Thank you for listening August 22, Master's Thesis Research Plan

August 22, 2011Master's Thesis Research Plan14

Background Electrocardiography (ECG) -Electrical activity of the heart -Used for diagnosis of heart disease ECG examination currently used -12-lead ECG The time required to put leads on the patient skin is only few minutes It is impossible to diagnose whether the patient’s heart is normal or not -Holter monitors Collecting ECG signals from the patient over a day Taking too hours to analyze ECG signals August 22, 2011Master's Thesis Research Plan15

Background (2) New ECG processing system is necessary -12-lead -Real time -small Processing ECG signals involves heavy computation Previous proposed ECG processing system - Parallel processing using additional cores for analyzing ECG signals August 22, 2011Master's Thesis Research Plan16

Research motivation Problems Input of current system is sample data already converted to digital -Impractical Parallelization adding additional cores -The more leads, the larger logic utilization Display of analysis results -Screen is too narrow to display a lot of results August 22, Master's Thesis Research Plan

System architecture August 22, 2011Master's Thesis Research Plan18 Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory ECG Data Rom : Data flow : Control signal : Data flow : Control signal

Background August 22, 2011Master's Thesis Research Plan19 ECG is used for diagnosis of heart disease Haga’s system processes ECG signals one single lead at a time Figure: Haga’s system architecture proposed last year ADC 1 ADC 12 FIR 1 FIR 12 Buffer ECG Signal Analysis 1:Signal reading 2:Filtering3:Analysis4:Display 12 leads External Memory Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms

Conclusion Previous proposed system is not high performance -Logic utilization is large -Processing time is not good Implementing A/D converters to the system -The system becomes practical Review of software code is needed - For parallelization August 22, Master's Thesis Research Plan