Computers organization & Assembly Language Chapter 1 THE 80x86 MICROPROCESSOR

Registers inside 8088/8086, IA-32 Instruction Execution Cycle IA-32 Memory Management 2

Computers Organization & Assembly Language 3 Inside the 8088/8086

4 Registers inside 8088/8086 Registers are used to store information temporarily. That information could be one or two bytes of data to be processed or the address of data. The general-purpose registers in 8088/86 microprocessors can be accessed as either 16-bit or 8-bit registers. All other registers can be accessed only as the full 16 bits. In the 8088/86. data types are either 8 or 16 bits. To access 12- bit data. for example, a 16-bit register must be used with the highest 4 bits set to 0.

5 Registers inside 8088/8086 In the 8088/86. data types are either 8 or 16 bits. To access 12-bit data. for example, a 16-bit register must be used with the highest 4 bits set to 0.

6 Registers inside 8088/8086 Category Registers8-bit Name16-bit Name General-Purpose AX – accumulator AH - ALAX BX – baseBH – BL BX CX – loop counterCH – CL CX DX – dataDH – DL DX Pointer SP – stack pointer -SP BP – base pointer -BP Index SI – source index -SI DI – destination index -DI Segment CS – code segment -CS DS – data segment -DS SS – stack segment -SS ES – extra segment -ES instruction IP – instruction pointer -IP Flag FLAGS-FR

Basic Program Execution Registers IA-32 CS SS DS ES EIP EFLAGS 16-bit Segment Registers EAX EBX ECX EDX 32-bit General-Purpose Registers FS GS EBP ESP ESI EDI Registers are high speed memory inside the CPU –Eight 32-bit general-purpose registers –Six 16-bit segment registers –Processor Status Flags (EFLAGS) and Instruction Pointer (EIP) 7

General-Purpose Registers Used primarily for arithmetic and data movement –mov eax, 10 move constant 10 into register eax Specialized uses of Registers –EAX – Accumulator register Automatically used by multiplication and division instructions –ECX – Counter register Automatically used by LOOP instructions –ESP – Stack Pointer register Used by PUSH and POP instructions, points to top of stack –ESI and EDI – Source Index and Destination Index register Used by string instructions –EBP – Base Pointer register Used to reference parameters and local variables on the stack 8

Accessing Parts of Registers EAX, EBX, ECX, and EDX are 32-bit Extended registers –Programmers can access their 16-bit and 8-bit parts –Lower 16-bit of EAX is named AX –AX is further divided into AL = lower 8 bits AH = upper 8 bits ESI, EDI, EBP, ESP have only 16-bit names for lower half 9

Accessing Parts of Registers 10

Special-Purpose & Segment Registers EIP = Extended Instruction Pointer –Contains address of next instruction to be executed EFLAGS = Extended Flags Register –Contains status and control flags –Each flag is a single binary bit Six 16-bit Segment Registers –Support segmented memory –Six segments accessible at a time –Segments contain distinct contents CodeDataStack

Floating-Point, MMX, XMM Registers Floating-point unit performs high speed FP operations Eight 80-bit floating-point data registers –ST(0), ST(1),..., ST(7) –Arranged as a stack –Used for floating-point arithmetic Eight 64-bit MMX registers –Used with MMX instructions Eight 128-bit XMM registers –Used with SSE instructions 12

Next... IA-32 Registers Instruction Execution Cycle IA-32 Memory Management 13

Fetch-Execute Cycle Each machine language instruction is first fetched from the memory and stored in an Instruction Register (IR). The address of the instruction to be fetched is stored in a register called Program Counter or simply PC. In some computers this register is called the Instruction Pointer or IP. After the instruction is fetched, the PC (or IP) is incremented to point to the address of the next instruction. The fetched instruction is decoded (to determine what needs to be done) and executed by the CPU. 14

Computers Organization & Assembly Language 15 Clock synchronizes all CPU and BUS operations machine (clock) cycle measures time of a single operation clock is used to trigger events

Instruction Execute Cycle Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value and status Deposit results in storage for later use Instruction Decode Instruction Fetch Operand Fetch Execute Writeback Result Infinite Cycle 16

Instruction Execution Cycle – cont'd Instruction Fetch Instruction Decode Operand Fetch Execute Result Writeback I2I3I4 PC program I1 instruction register op1 op2 memory fetch ALU registers write decode execute read write (output) registers flags... I1 17

18 Pipelining There are two ways to make the CPU process information faster: – –increase the working frequency – –or change the internal architecture of the CPU. (Pipelining) Pipelining is allow the CPU to fetch and execute at the same time. Pipelining in the 8088/86 by splitting the internal structure of the microprocessor into two sections: the execution unit (EU) and the bus interface unit (BIU). These two sections work simultaneously. The BIU accesses memory and peripherals while the EU executes instructions previously fetched. This works only if the BIU keeps ahead of the EU; thus the BIU of the 8088/86 has a buffer, or queue. The buffer is 4 bytes long in the 8088 and 6 bytes in the If any instruction takes too long to execute, the queue is filled to its maximum capacity and the buses will sit idle. The BIU fetches a new instruction whenever the queue has room for 2 bytes in the 6-byte 8086 queue, and for 1 byte in the 4-byte 8088 queue.

19 Pipelined vs. Nonpipelined

Pipelined Execution Instruction execution can be divided into stages Pipelining makes it possible to start an instruction before completing the execution of previous one Non-pipelined execution Wasted clock cycles Pipelined Execution For k stages and n instructions, the number of required cycles is: k + n – 1 20

 Assume that stage S4 is the execute stage  Assume also that S4 requires 2 clock cycles to complete  As more instructions enter the pipeline, wasted cycles occur  For k stages, where one stage requires 2 cycles, n instructions require k + 2n – 1 cycles Wasted Cycles (pipelined) When one of the stages requires two or more clock cycles to complete, clock cycles are again wasted 21

Superscalar Architecture A superscalar processor has multiple execution pipelines The Pentium processor has two execution pipelines –Called U and V pipes In the following, stage S4 has 2 pipelines –Each pipeline still requires 2 cycles –Second pipeline eliminates wasted cycles –For k stages and n instructions, number of cycles = k + n 22

23 Introduction to Assembly Language MOV instruction MOV instruction copies data from one location to another. It has the following format: MOV destination, source copy source operand to destination This instruction tells the CPU to move (in reality, copy) the source operand to the destination operand. For example, MOV DX, CX copies the contents of register CX to register DX. After this instruction is executed, register DX will have the same value as register CX. The MOV instruction does not affect the source operand.

24 MOV Examples MOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOV CL, 55H DL, CL AH, DL AL, AH BH, CL CH, BH CX, 468FH AX, CX DX, AX BX, DX DI, BX SI, DI DS, SI BP, DI ;move 55H into register CL ;copy the contents of CL into DL (now DL=CL=55H) ;copy the contents of DL into AH (now AH=DL=55H) ;copy the contents of AH into AL (now AL=AH=55H) ;copy the contents of CL into BH (now BH=CL=55H) ;copy the contents of BH into CH (now CH=BH=55H) ;move 468FH into CX (now CH = 46, CL = 8F) ;copy contents of CX to AX (now AX = CX = 468FH) ;copy contents of AX to OX (now DX = AX = 468FH) ;copy contents of OX to BX (now BX = DX = 468FH) ;now DI = BX = 468FH ;now SI = DI = 468FH ;now DS = SI = 468FH ;now BP = DI = 468FH

25 MOV Instruction Data can be moved among all the register as long as the source and destination registers match in size. MOV AL, DX; Error Data can not be moved directly into segment registers. MOV DS, 2459H; Error Values cannot be loaded directly into any segment register (CS, DS, ES, or SS). To load a value into a segment register, first load it to a nonsegment register and then move it to the segment register. MOV AX, 2345H;Ioad 2345H into AX MOV DS, AX ;load the value of AX into DS If a value less than FFH is moved into a 16-bit register, the rest of the bits are assumed to be all zeros. MOV BX, 5 ;the result will be BX = 0005; Moving a value that is too large into a register will cause an error. MOV BL, 7F2H;ILLEGAL: 7F2H is larger than 8 bits MOV AX, 2FE456H;ILLEGAL: the value is larger than AX

26 ADD instruction ADD instruction has the following format: ADD destination, source The ADD instruction adds the source and destination operands and put the result in the destination. To add two numbers such as 25H and 34H: MOV AL, 25H;move 25 into AL MOV BL, 34H;move 34 into BL ADD AL, BL;AL = AL + BL The program above can be written in many ways, MOV DH, 25H;move 25 into DH MOV CL, 34H;move 34 into CL ADD DH, CL;add CL to DH; DH = DH+CL Another way: MOV DH, 25H;Ioad one operand into DH ADD DH, 34H;add the second operand to DH

27 ADD instruction The largest number that an 8-bit register can hold is FFH. To use numbers larger than FFH (255 decimal), 16-bit registers such as AX, BX, ex, or DX must be used. For example, to add two numbers such as 34EH and 6A5H, the following program can be used: MOV AX, 34EH ;move 34EH into AX MOV DX, 6ASH ;move 6A5H into DX ADD DX, AX;add AX to DX Again, any 16-bit non segment registers could have been used to perform the action above: MOV CX, 34EH;Ioad 34EH into CX ADD CX, 6A5H;add 6A5H to CX

Computers Organization & Assembly Language 28 Flag Register in 8086/8086 The flag register is a 16-bit register sometimes referred to as the status register Although the register is 16 bits wide, only some of the bits are used. The rest are either undefined or reserved by Intel. Six of the flags are called conditional flags, meaning that they indicate some condition that resulted after an instruction was executed. These six are CF, PF, AF, ZF, SF, and OF. The three remaining flags are sometimes called control flags since they are used to control the operation of instructions before they are executed.

Introduction to Microprocessors & Assembly Language 29 Flag Register in 8086/8086

EFLAGS Register in AI-32  Status Flags  Status of arithmetic and logical operations  Control and System flags  Control the CPU operation  Programs can set and clear individual bits in the EFLAGS register 30

Status Flags CF, Carry Flag –Set when unsigned arithmetic result is out of range OF, Overflow Flag –Set when signed arithmetic result is out of range SF, Sign Flag –Copy of sign bit, set when result is negative ZF, Zero Flag –Set when result is zero AF, Auxiliary Carry Flag –Set when there is a carry from bit 3 to bit 4 PF, Parity Flag –Set when parity is even –Least-significant byte in result contains even number of 1s TF, the Trap Flag. Set to perform single-step execute IF, Interrupt Enable Flag. indicating the external maskable interrupt requests. DF, the Direction Flag. This bit is used to control the direction of string operations, OF, the Overflow Flag. This flag is set whenever the result of a signed number overflow 31

Computers Organization & Assembly Language 32 Example 1-10 Show how the flag register is affected by the addition of 38H and 2FH. Solution MOV BH, 38H;BH= 38H ADD BH, 2FH;add 2F to BH, now BH=67H F CF = 0 since there is no carry beyond d7 PF = 0 since there is an odd number of Is in the result AF = 1 since there is a carry from d3 to d4 ZF = 0 since the result is not zero SF = 0 since d7 of the result is zero 111

Computers Organization & Assembly Language 33 Example 1-11 Show how the flag register is affected by MOV AL, 9CH;AL = 9CH MOV DH, 64H;DH = 64H ADD AL, DH;now AL = 0 Solution 9C CF = 1 since there is carry beyond d7 PF = 1 since there is an odd number of Is in the result AF = 1 since there is a carry from d3 to d4 ZF = 1 since the result is zero SF = 0 since d7 of the result is zero 11111

34 The End