George Mason University Controllers for Keccak_F and AES ECE 545 Lecture 11 Addendum

ECE 448 – FPGA and ASIC Design with VHDL Keccak_F

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Keccak_F_Control is generic ( G_RNDS : integer := 24 --! Number of round_rs for the permutation ); port ( --! Global signals clk : in std_logic; rst : in std_logic; --! External signals start : in std_logic; --! Start signal ready : out std_logic; --! Ready signal done : out std_logic; --! Done signal --! Internal signals round : out std_logic_vector(4 downto 0); sel_in : out std_logic; en_in : out std_logic ); end Keccak_F_Control;

architecture behav of Keccak_F_Control is type type_state is (S_RESET, S_WAIT_START, S_PROCESS, S_DONE); signal state : type_state; signal state_next : type_state; signal round_r : std_logic_vector(4 downto 0); signal round_next : std_logic_vector(4 downto 0); begin pctrl: process( clk ) begin if rising_edge( clk ) then if rst = '1' then state <= S_RESET; round_r '0'); else state <= state_next; round_r <= round_next; end if; end process; round <= round_r;

pcomb: process(state, round_r, start) begin --! Default values state_next<= state; round_next<= round_r; ready <= '0'; sel_in <= '0'; en_in <= '0'; done <= '0'; case state is when S_RESET => round_next '0'); state_next <= S_WAIT_START; when S_WAIT_START => ready <= '1'; if (start = '1') then en_in <= '1'; sel_in <= '1'; round_next <= round_r + 1; state_next <= S_PROCESS; end if;

when S_PROCESS => en_in <= '1'; if (round_r = G_RNDS-1) then round_next '0'); state_next <= S_DONE; else round_next <= round_r + 1; end if; when S_DONE => done <= '1'; ready <= '1'; if (start = '1') then en_in <= '1'; sel_in <= '1'; round_next <= round_r + 1; state_next <= S_PROCESS; else state_next <= S_WAIT_START; end if; end case; end process; end behav;

11ECE 448 – FPGA and ASIC Design with VHDL AES_Enc

Registered Outputs done_s and done_init_s are outputs of the Mealy type done and done_init are the corresponding outputs of the Moore type done and done_init become active at the rising edge of the clock if done_s and done_init_s are already active when this edge happens Pulses at the outputs done_s and done_init_s last for a fraction of a clock period. Pulses at the outputs done and done_init last for the entire following clock period.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.aes_pkg.all; entity AES_Enc_Control is generic ( G_RNDS : integer := AES_ROUNDS); port( clk : in std_logic; rst : in std_logic; start: in std_logic; init: in std_logic; sel_fkey: out std_logic; en_fkey: out std_logic; en_rkey: out std_logic; wr_rkey: out std_logic; round: out std_logic_vector(3 downto 0); sel_in: out std_logic; en_in: out std_logic; ready: out std_logic; done: out std_logic; done_init: out std_logic); end AES_Enc_Control;

architecture behav of AES_Enc_Control is type t_state is (S_RESET, S_WAIT_START, S_INIT, S_PROCESS); signal state : t_state; signal state_next : t_state; signal round_r : std_logic_vector(3 downto 0); signal round_next : std_logic_vector(3 downto 0); signal done_s : std_logic; signal done_init_s : std_logic; begin p_fsm: process(clk) begin if rising_edge(clk) then if (rst = '1') then state <= S_RESET; else state<= state_next; end if; round_r<= round_next; done<= done_s; done_init<= done_init_s; end if; end process; round <= round_r;

p_comb: process(state, round_r, init, start) begin --! Default values state_next <= state; round_next <= round_r; ready <= '0'; en_fkey<= '0'; wr_rkey <= '0'; sel_fkey <= '0'; sel_in <= '0'; en_in <= '0'; en_rkey <= '0'; done_init_s <= '0'; done_s <= '0'; case state is when S_RESET => state_next <= S_WAIT_START; round_next '0');

when S_WAIT_START => ready <= '1'; if (init = '1') then en_fkey <= '1'; state_next <= S_INIT; elsif (start = '1') then sel_in<= '1'; en_in<= '1'; en_rkey<= '1'; round_next<= round_r + 1; state_next<= S_PROCESS; end if; when S_INIT => wr_rkey <= '1'; if (round_r = G_RNDS-1) then round_next '0'); done_init_s<= '1'; state_next<= S_WAIT_START; else if (round_r = 0) then sel_fkey <= '1'; end if; round_next<= round_r + 1; end if;

when S_PROCESS => en_rkey <= '1'; en_in <= '1'; if (round_r = G_RNDS-1) then round_next '0'); done_s <= '1'; state_next <= S_WAIT_START; else round_next <= round_r + 1; end if; end case; end process; end behav;

Advanced Coding Style for the Datapath

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.aes_pkg.all; entity AES_Enc_Datapath is port( clk : in std_logic; rst : in std_logic; din : in t_AES_state; key : in t_AES_state; dout : out t_AES_state; sel_fkey : in std_logic; en_fkey : in std_logic; en_rkey : in std_logic; wr_rkey : in std_logic; round : in std_logic_vector(3 downto 0); sel_in : in std_logic; en_in : in std_logic); end AES_Enc_Datapath;

architecture structure of AES_Enc_Datapath is signal from_reg : t_AES_state; signal from_round_fdb : t_AES_state; signal ki_state : t_AES_state; signal ko_state : t_AES_state; signal fkey : t_AES_state; signal rkey_state : t_AES_state; signal ko_reg : t_AES_state; signal ko : std_logic_vector(AES_BLOCK_SIZE-1 downto 0); signal rkey : std_logic_vector(AES_BLOCK_SIZE-1 downto 0); type t_key_ram is array (0 to 15) of std_logic_vector(AES_BLOCK_SIZE-1 downto 0); signal key_ram : t_key_ram; begin u_inv_ko: entity work.AES_invmap(structure) port map ( ii => ko_state, oo => ko); u_map_rkey: entity work.AES_map(structure) port map ( ii => rkey, oo => rkey_state);

p_reg: process(clk) begin if rising_edge(clk) then if en_in = '1' then if sel_in = '1' then for i in 0 to 3 loop for j in 0 to 3 loop from_reg(j,i) <= din(j,i) xor fkey(j,i); end loop; else from_reg <= from_round_fdb; end if; if en_fkey = '1' then fkey <= key; end if;

if wr_rkey = '1' then key_ram(to_integer(unsigned(round))) <= ko; ko_reg <= ko_state; end if; if en_rkey = '1' then rkey <= key_ram(to_integer(unsigned(round))); end if; end process;

u_round: entity work.AES_Round(basic) port map ( din => from_reg, rkey => rkey_state, dout_fdb => from_round_fdb, dout => dout); --! Key Expansion ki_state <= fkey when sel_fkey = '1' else ko_reg; u_keyexp: entity work.AES_KeyUpdate(key_size_128) port map ( round => round, ki => ki_state, ko => ko_state); end structure;

ECE 448 – FPGA and ASIC Design with VHDL AES_EncDec

Using a Pulse to Store the Current Value of an Input decrypt is an input to FSM that lasts for just one clock cycle we store its value for future use in the register decrypt_r, as represented in the ASM chart using the action decrypt_r = decrypt in order to perform this action in the VHDL code, the assignment decrypt_r = decrypt is represented as an active value of the enable signal of the register decrypt_r, called en_decrypt_s

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.AES_pkg.all; entity AES_EncDec_Control is generic ( G_RNDS : integer := AES_ROUNDS); port( clk: in std_logic; rst: in std_logic; --! Internal sel_decrypt: out std_logic; invround: out std_logic_vector(3 downto 0); round: out std_logic_vector(3 downto 0); en_rkey: out std_logic; wr_rkey: out std_logic; en_fkey: out std_logic; en_lkey: out std_logic; sel_fkey: out std_logic; sel_round: out std_logic; sel_in: out std_logic_vector(1 downto 0); en_in: out std_logic;

--! External init : in std_logic; done_init: out std_logic; start: in std_logic; decrypt: in std_logic; ready: out std_logic; done: out std_logic); end AES_EncDec_Control;

architecture behav of AES_EncDec_Control is --! Internal Registers type t_state is (S_RESET, S_WAIT_START, S_INIT_KEY, S_PROCESS); signal state : t_state; signal state_next : t_state; signal round_r : std_logic_vector(3 downto 0); signal round_next : std_logic_vector(3 downto 0); signal invround_r : std_logic_vector(3 downto 0); signal invround_next : std_logic_vector(3 downto 0); signal decrypt_r : std_logic; signal done_r : std_logic; signal done_init_r : std_logic; --! Internal signals signal en_decrypt_s : std_logic; signal done_s : std_logic; signal done_init_s : std_logic;

begin p_fsm: process(clk) begin if rising_edge(clk) then if (rst = '1') then state <= S_RESET; else state <= state_next; end if; if (en_decrypt_s = '1') then decrypt_r <= decrypt; end if; round_r<= round_next; invround_r <= invround_next; done_init_r <= done_init_s; done_r <= done_s; end if; end process; round <= round_r; invround <= invround_r; sel_decrypt <= decrypt_r; done_init <= done_init_r; done <= done_r;

p_comb: process(state, round_r, init, start, decrypt_r, decrypt) begin --! Default values state_next <= state; round_next <= round_r; ready <= '0'; en_lkey<= '0'; en_fkey<= '0'; wr_rkey<= '0'; sel_fkey<= '0'; sel_in<= "00"; en_in<= '0'; sel_round<= '0'; en_rkey<= '0'; en_decrypt_s<= '0'; done_s<= '0'; done_init_s<= '0'; case state is when S_RESET => round_next <= std_logic_vector(to_unsigned(1,4)); invround_next <= std_logic_vector(to_unsigned(G_RNDS-1,4)); state_next <= S_WAIT_START;

when S_WAIT_START => ready <= '1'; if (init = '1') then round_next '0'); en_lkey<= '1'; en_fkey<= '1'; state_next <= S_INIT_KEY; elsif (start = '1') then en_decrypt_s<= '1'; sel_in <= "10"; en_in<= '1'; en_rkey<= '1'; if (decrypt = '1') then sel_round <= '1'; else sel_fkey <= '1'; end if; round_next<= round_r + 1; invround_next<= invround_r - 1; state_next<= S_PROCESS; end if;

when S_INIT_KEY => wr_rkey <= '1'; if (round_r = 0) then sel_fkey <= '1'; end if; if (round_r = G_RNDS) then round_next <= std_logic_vector(to_unsigned(1,4)); done_init_s <= '1'; state_next <= S_WAIT_START; else round_next <= round_r + 1; en_lkey <= '1'; end if;

when S_PROCESS => en_rkey <= '1'; en_in <= '1'; if (decrypt_r = '1') then sel_round <= '1'; sel_in <= "01"; end if; if (round_r = G_RNDS) then round_next <= std_logic_vector(to_unsigned(1,4)); invround_next <= std_logic_vector(to_unsigned(G_RNDS-1,4)); done_s <= '1'; state_next <= S_WAIT_START; else round_next <= round_r + 1; invround_next <= invround_r - 1; end if; end case; end process; end behav;