Interconnect/Via

Delay of Devices and Interconnect

Reduction of the feature size Increase in the influence of the interconnect delay on system performance Skew The difference in the arrival times of the clock signal to all registers in a synchronous digital system

An Example , The Clock Distribution Network (CDN) A set of interconnections that delivers reliably a time reference, clock signal , to every register element in a synchronous digital system. PowerPC microprocessor 32,000 master/slave latch

Power Consumption &Routing and system complexity P= CV2f Memory Leakage Short-Circuit Clock I/O Global Interconnect Logic and Local Routing

Delay model of the CDN, Elmore Delay model er0 It takes into account the interconnect resistance and capacitance and the capacitance of the registers r1 r2 s1 r4 r3 s2 s0 s1 r1 r2 s2 r3 r4 s0

Example: Routing delay problems The Clock Skew Out In Ri Rj Ti Tj TPD(min) /TPD(max) The difference between time arrivals of the clock signal to all the registers in a synchronous digital system S(ij) = Ti - Tj Two conditions: Clock Period Limitations Permissible range Race Conditions S(ij)min S(ij)max S(ij)  THOLDj - TPD(min) S(ij)  Tclk - TPD(max)

Minimizing the effects of delay, The H_Tree If it is possible to divide the set of registers R into two symmetric sets recursively and alternatively by vertical and horizontal lines, then the set R can be connected by an H-tree

Interconnect Length

Interconnect/Via

Cross Section View of Capacitances in interconnect Units are in Angstrom, 1A=0.1nm

Interconnect Interconnects in chips are routed in several layers horizontally and vertically and used according to their application

Parallel and fringing Capacitance

Fringing Capacitance T is the thickness of wire H is the distance of wire to substrate.

Cross Talk

Fringing/ Parallel Plate Capacitance of Interconnect

Modeling Interconnect LUMPED MODEL T-MODEL -MODEL 2T-MODEL 2π -MODEL

Modeling of Interconnect

Delay of Interconnect Capacitance = C/unit area * L (length) * W (width) = C Resistance = R/ * number of squares = R

Delay comparison

Calculate the delay and comment on methods for reducing this delay. Example A signal is propagated on a 6mm length metal 1 (M1) interconnect of CMOSIS5 Process, using minimum wire width. Calculate the delay and comment on methods for reducing this delay. 6mm

Different Path

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What is the maximum size of silicon chip? Power dissipation Packaging Number of pins Technology The interconnect used

Inductances For die wires h is the height of the wire above the substrate, d is the diameter of the wire is the magnetic permeability of the material

Inductance For on-chip, h is the height of the wire above the substrate, d is the diameter of the wire is the magnetic permeability of the material

Example on VDD Bounce Determine the values of due to inductive and resistive losses when the output driver sources 10mA in 1.5ns in the following circuit.

What will be the power line width if you drive a 10pF load at 1GHz Example on Power lines What will be the power line width if you drive a 10pF load at 1GHz Assume Vdd=3.5V.

Example on Charge Sharing Calculate the drop in voltage for 64 read lines each consisting of 0.1pF capacitances. Assume bus capacitance to be 10pF.

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