Technical University Tallinn, ESTONIA Component level dy Defect mapping Hierarchical Test Generation x1x1 x2x2 x3x3 x4x4 x5x5 System level WdWd Logic level Error Defect Hierarchical test (fault propagation) y* & & & 1 & & & Logic level Transistor level RT Level

Technical University Tallinn, ESTONIA Binary Decision Diagrams Simulation: Boolean derivative: y x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 x7x Functional BDD

Research in ATI © Raimund Ubar Generalization of BDDs m y 1 0 lmlm l1l1 l0l0 GyGy m Y h FkFk FnFn l0l0 l1l1 l2l2 lhlh lklk l k+1 F k+1 lnln lmlm GYGY Binary DD 2 terminal nodes and 2 edges from each node General case of DD n  2 terminal nodes and n  2 edges from each node Novelty: Boolean methods can be generalized in a straightforward way to higher functional levels 3

Technical University Tallinn, ESTONIA Faults and High-Level Decision Diagrams RTL-statement: Terminal nodes RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults K: ( If T,C) R D  F(R S1,R S2,…R Sm ),  N

Technical University Tallinn, ESTONIA 5 Fault Modeling on DDs Each path in a DD describes the behavior of the system in a specific mode of operation The faults having effect on the behaviour can be associated with nodes along the path A fault causes incorrect leaving the path activated by a test

Technical University Tallinn, ESTONIA 6 Uniform Formal Fault Model on DDs D1: the output edge for x(m) = i of a node m is always activated D2: the output edge for x(m) = i of a node m is broken D3: instead of the given edge, another edge or a set of edges is activated

Technical University Tallinn, ESTONIA Fault Collapsing with SSBDDs Each node in SSBDD represents a signal path: Two SSBDD faults x 11  1, x 11  0 represent a set of six faults in the circuit: {x 11  1, x 6  1, y  1; x 11  0, x 6  0, y  0}

Research in ATI © Raimund Ubar Each node in SSBDD represents a signal path: The faults at y 3 in HLDD represent the faults in the control circuitry and in the multiplexer M3 of the RTL circuit The faults at R1*R2 in HLDD represent the faults in multiplier, input and output buses, and in the registers Structural HLDDs Fault collapsing – not investigated at high-level

Technical University Tallinn, ESTONIA Decision Diagrams for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  IA I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A Instruction set: IA 2 R IN 5 R 1,3,4,6-10 AIIN 1,6 IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 IR 3 A OUT 4 DD-model of the microprocessor:

Technical University Tallinn, ESTONIA Decision Diagrams for Microprocessors High-Level DD-based structure of the microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: OUT R A IN I

Research in ATI © Raimund Ubar 11 OPBSemanticRT level operations 0 0READ memoryR(A1) = M(A)PC = PC + 2 1WRITE memoryM(A) = R(A2)PC = PC TransferR(A1) = R(A2)PC = PC + 1 1Complement R(A1) =  R(A2) PC = PC AdditionR(A1) = R(A1)+ R(A2)PC = PC + 1 1SubtractionR(A1) = R(A1)- R(A2)PC = PC JumpPC = A 1Conditional jumpIF C=1, THEN PC = A,ELSE PC = PC + 2 From MP Instruction Set to HLDDs OP B 0 M(A) 1 R(A2) M(A) OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 A1 = 0 R0R0 R0R0 0 1 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 OP B0B0 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 R(A1) R(A1) + R(A2) R(A1) Instruction code: ADD A1 A2 OP=2. B=0. A1=3. A2=2 R 3 = R 3 + R 2 PC = PC+1

Research in ATI © Raimund Ubar 12 HLDDs for MP InstrSet A1 = 0 R0R0 R0R0 0 OP B0B0 1 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B R(A1) - R(A2) 3 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 R(A1) R(A1) + R(A2) R(A1) Registers and ALU A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 Register Decoding OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C Program Counter OP B 0 M(A) 1 R(A2) M(A) Memory Access Instruction code: ADD A1 A2 OP=2. B=0. A1=3. A2=2 R 3 = R 3 + R 2 PC = PC+1

Technical University Tallinn, ESTONIA Structural Synthesis of HLDDs Data Path Control Path y x

Technical University Tallinn, ESTONIA Data Path: High-Level DD Synthesis Data Path Control Path y x y 4 e R  0 R 2

Technical University Tallinn, ESTONIA Data Path: HLDD Synthesis Data Path Control Path y x y 4 y 3 c d R  0 R 2 IN R R2R2 R 2 + e

Technical University Tallinn, ESTONIA Data Path: HLDD Synthesis y 1 R 1 + R 2 IN + R 2 R 1 * R 2 IN* R 2 y IN R y 4 y 3 R  0 R 2 R2R2 R 2 + M 3 c (M 1 ) d (M 2 )

Technical University Tallinn, ESTONIA High-Level Decision Diagrams Superposition of High-Level DDs: A single DD for a subcircuit Instead of simulating all the components in the circuit, only a single path in the DD should be traced y 4 y 3 y 1 R 1 + R 2 IN + R 2 R 1 * R 2 IN* R 2 y 2 R  0 R 2 IN R R2R2 R 2 + M 3 M1M1 M2M2

Technical University Tallinn, ESTONIA BDDs for Flip-Flops – Functional Synthesis D C qc q’ D Elementary BDDs D Flip-Flop S J q R C K JK Flip-Flop c q’ S R q’q’ K J S C q R c S R q’q’ R U RS Flip-Flop U - unknown value BDDs as a method for knowledge presentation

Technical University Tallinn, ESTONIA Functional Synthesis of High-Level DDs Data-Flow Diagram High-Level DDs can be synthesized by symbolic execution of the Data-Flow Diagram F2

Technical University Tallinn, ESTONIA Synthesis of High-Level DDs High-Level DDs can be synthesized by symbolic execution of the Data-Flow Diagram: F2AXAC AX AC=0 PC PC+1 Decision Diagrams: F0AC AC+1 F2 AC AX F

Research in ATI © Raimund Ubar Digital System and Data Flow Diagram A B C M ADR MUX 1 2 CC CON D Control Path Data Path  / FF y x q q z z 1 z 2 Digital system Data-Flow Diagram

Research in ATI © Raimund Ubar Functional HLDDs Data Flow Diagram Decision Diagrams Register variables State variable

Research in ATI © Raimund Ubar Synthesis of Functional HLDDs Data Flow Diagram/FSMD Begin A = B + C x A A =  A + 1 B = B + C x A B =  BC =  C x B  C x C A = A +  B + C x C C = A + B A =  C + B END Constraints Assignment statements qxAxA xBxB xCxC 0 A = B + C; q = 1 10 A = A + 1; q = 4 11 B = B + C; q = 2 20 C = A + B; q = 5 21 C = C; q = 3 30 C = A + B; q = 5 31 A = C + B; q = 5 40 B = B 400 A = A + B + C; q = q = 5 41 C = C; q = 5 Results of cycle based symbolic simulation: q = 0 q = 1 q = 2 q = 3 q = 4 q = 5

Research in ATI © Raimund Ubar Synthesis of HLDDs Constraints Assignment statements qxAxA xBxB xCxC 0 A = B + C; q = 1 10 A = A + 1; q = 4 11 B = B + C; q = 2 20 C = A + B; q = 5 21 C = C; q = 3 30 C = A + B; q = 5 31 A = C + B; q = 5 40 B = B 400 A = A + B + C; q = q = 5 41 C = C; q = 5 Results of symbolic simulation: qxAxA xBxB xCxC A 0B + C 10 A C + B 400 A + B + C Extraction of the behaviour for A: A = f (q, A, B, C, x A, x C ) = = (q=0)(B+C)  (q=1)(x A =0) (  A + 1)  (q=3)(x C =1)(  C+B)  (q=4)(x A =0)(x C =0)(A+  B + C + 1) Predicate equation for A:

Research in ATI © Raimund Ubar Synthesis of HLDDs qxAxA xBxB xCxC A 0B + C 10 A C + B 400 A + B + C Extraction of the behaviour for A: A = (q=0)(B+C)  (q=1)(x A =0) (  A + 1)  (q=3)(x C =1)(  C+B)  (q=4)(x A =0)(x C =0)(A+  B + C + 1) Predicate equation for A: Decision diagram for A: Synthesis method: similar to Shannon’s expansion theorem:

Research in ATI © Raimund Ubar Functional HLDDs Data Flow Diagram Decision Diagrams Register variables State variable

Research in ATI © Raimund Ubar High-Level Vector Decision Diagrams 3,4 0 2 q q  1  4 x A  2 1  5 x B  3 A q x A B + C  A x C  C + B 0 4 x A A + C B q x A B + C  B C 14 2 q x A 1 0 x B A + B  C 0 x C x A 1 x C 3 0 M=A.B.C.q 1 1 q x A 0 q A i B’ + C’ #1 q B i B’ + C’ #2 0 q A i  A’ + 1 #4 2 1 x B q C i  C’ #3 0 q C i A’ + B’ #5 3 1 x C q A i B’ +  C’ #5 0 q C i A’ + B’ #5 4 1 x C q C i  C’ #5 0 B A i A’ + B’+C’ x A 0 q #5  B’ q B i  #5 A system of 4 DDsVector DD

Technical University Tallinn, ESTONIA DD Synthesis from VHDL Descriptions VHDL description of 4 processes which represent a simple control unit

Technical University Tallinn, ESTONIA DD Synthesis from VHDL Descriptions nstate rst clk  #1 state’ state clk enable’ enable 1 enable_in 0 DDs for state, enable_in and nstate state’ rb0 enable_in #2 # nstate Superposition of DDs

Technical University Tallinn, ESTONIA DD Synthesis from VHDL Descriptions rst #1 state1 0 state’ rb0 enable' #2 # enable #0011 # enable #0100 # state rb # outreg fin reg_cp reg DDs for the total VHDL model

Technical University Tallinn, ESTONIA DD Synthesis from VHDL Descriptions rst #1 state1 0 state’ rb0 enable' #2 # enable #0011 # enable #0100 # state rb # outreg fin reg_cp reg Simulation and Fault Backtracing on the DDs Simulated vector

Technical University Tallinn, ESTONIA 32 Hierarchical Modelling on DDs M=A.B.C.q 1 1 q x A 0 q A i B’ + C’ #1 q B i #2 0 q A i  A’ + 1 #4 2 1 x B q C i  C’ #3 0 q C i A’ + B’ #5 3 1 x C q A i B’ +  C’ #5 0 q C i A’ + B’ #5 4 1 x C q C i  C’ #5 0 B A i A’ + B’+C’ x A 0 q #5  B’ q B i  #5 x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 x7x C Component: Binary Decision Diagram System: High-level decision diagram A small part is simulated at the higher level: to increase the speed of analysis A small part is simulated at the lower level Cause-effect analysis well formalized B’ + C’