C. Combaret 27 jan 2010 SDHCAL Power pulsing tests status in lyon C. Combaret, for the IPNL team.

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Presentation transcript:

C. Combaret 27 jan 2010 SDHCAL Power pulsing tests status in lyon C. Combaret, for the IPNL team

C. Combaret 27 jan 2010 Power pulsing on Hardroc 2 ASU : method As discussed with HR2 designers : 1.Record (reference) Scurves and Bias levels with no capacitor removed 2.Enable PP hardware on DIF (use of Mezzanine pin 1) 3.Enable PP in DIF firmware : PowerOn_x = register OR Mezzanine_1 4.Try PP with no capacitor removed 5.Record analog bias signal 6.Remove Capacitors on biases of 1 HR2 step by step and check 7.Record analog bias signal 8.Record Scurves 9.Remove Capacitors on biases of all asics and check again 10.Record analog bias signal 11.Record Scurves

C. Combaret 27 jan 2010 Hardware setup HP33220A HP33250A HP81104 Trg ext (Lemo2) Sync Trg ext Sync Trg ext Enable PP (Mezzanine) Enable Acq (Mezzanine) Ctest Lemo1 DIF Lemo2 Enable PP Enable Acq Lemo1 cTest

C. Combaret 27 jan 2010 Power pulsing on Hardroc 2 ASU : method

C. Combaret 27 jan 2010 Power pulsing on Hardroc 2 ASU : preliminary results Vbg (BandGap) PowerOn Command 10us Capacitors removed on one asic (first of the ASU)

C. Combaret 27 jan 2010 Power pulsing on Hardroc 2 ASU : preliminary results Vth 0 PowerOn Command <20us Capacitors removed on one asic (first of the ASU)

C. Combaret 27 jan 2010 Power pulsing on Hardroc 2 ASU : preliminary results Capacitors removed on all asics Trig_ext (Lemo1) Enable Acq Enable PP Vth2 Power On Power Off 50 µs

C. Combaret 27 jan 2010 Power pulsing on Hardroc 2 ASU : preliminary results DAC1Min = 80 DAC1Max =400 DAC1Step=1 GainMin = 128 GainMax = 128 GainStep=1 Injection=0.5V Pedestal looks roughly OK Injected channel seems rougly OK BUT strange behaviour for injected pads.  Because of slow control bug in HR2, some (many) SLC configurations can not be used

C. Combaret 27 jan 2010 Power pulsing on Hardroc 2 ASU : preliminary results After correction, data seem more correct… But this Scurve is very preliminary, comparisons must be made with results obtained before power pulsing. Asic 1 DAC1Min = 80 DAC1Max =400 DAC1Step=1 GainMin = 128 GainMax = 128 GainStep=1 Injection=0.5V

C. Combaret 27 jan 2010 DIF (For J. Prast, LAPP) VHDL firmware1 for Hardroc1 Micromegas VHDL firmware2 for Hardroc1 RPC VHDL firmware3 for Dirac2 Micromegas VHDL firmware4 for Hardroc2 Micromegas VHDL firmware5 for Calice DAQ Test

C. Combaret 27 jan 2010 DHCAL DIF Production (For J. Prast, LAPP) 120 DIF have to be produced for the m 3 (+ spares ie 140 ?). The DIF will be produced as they are currently. –The board works quite well. –We do not have time to make a new prototype (schedule + manpower). Boards will be produced and tested for beginning of fall –Some boards can be available before if required (> end of spring)

C. Combaret 27 jan 2010 Thank you for your attention