VHDL for Sequential Logic

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Presentation transcript:

VHDL for Sequential Logic ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning ELEC 311

D Flip-Flop 311_17 ELEC 311

Asynchronous Clear 311_17 ELEC 311

Shift Register 311_17 ELEC 311

Counter 311_17 ELEC 311

Design Example T-bird Tail Lights Left Turn Right Turn Hazard 311_17 ELEC 311

Flashing Sequence 311_17 ELEC 311

Flashing Sequence Left Turn Right Turn 311_17 ELEC 311

Initial State Graph Mutual Exclusion? All Inclusion? 311_17 ELEC 311

Corrected State Graph Handles multiple inputs asserted simultaneously 311_17 ELEC 311

Enhanced State Graph Goes into hazard mode as soon as possible 311_17 ELEC 311

VHDL Model entity TBIRD is port (clock, left, right, haz : in std_logic; tail : out std_logic_vector (1 to 6)); end TBIRD; architecture BEHAVE of TBIRD is type State_type is (IDLE,L1,L2,L3,R1,R2,R3,LR3); signal State, Next_State: State_type; signal input: std_logic_vector(1 to 3); begin input <= left & right & haz; 311_17 ELEC 311

VHDL Outputs with State select tail <= "000000" when IDLE, "001000" when L1, "011000" when L2, "111000" when L3, "000100" when R1, "000110" when R2, "000111" when R3, "111111" when LR3; 311_17 ELEC 311

VHDL Sequential Machine process (input, State) begin case State is when IDLE => case input is when "010" => Next_State <= R1; when "100" => Next_State <= L1; when "--1" => Next_State <= LR3; when others => Next_State <= IDLE; end case; when L1 => when others => Next_State <= L2; 311_17 ELEC 311

VHDL Sequential Machine process (SLOW_CLK) begin if SLOW_CLK'event and SLOW_CLK = '1' then State <= Next_State; end if; end process; 311_17 ELEC 311

Summary Sequential VHDL Design Example process if-then-else case 311_17 ELEC 311