FGM peer PDR I/F - 1 Braunschweig, October 8-9, 2003 Digital Interface (I/F) Aris Valavanoglou Institut für Weltraumforschung (IWF) Austrian Academy of.

Slides:



Advertisements
Similar presentations
Serial Interface Dr. Esam Al_Qaralleh CE Department
Advertisements

Generic Remote Interface Unit (RIU) Interface Control Document (ICD) CCSDS SOIS 2013 spring meeting Glenn Rakow/NASA-GSFC.
Digital Computer Fundamentals
Synchronous Counters with SSI Gates
1 EE24C Digital Electronics Project Theory: Sequential Logic (part 2)
ECT 357 Ch 18 UART. Today’s Quote: Be careful that your marriage doesn’t become a duel instead of a duet. Be careful that your marriage doesn’t become.
PH4705 ET4305 Interface Standards A number of standard digital data interfaces are used in measurement systems to connect instruments and computers for.
1 COMP541 Keyboard Interface Montek Singh April 9, 2007.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Senior Design I Lecture 11 - Data Communications.
Network Data Organizational Communications and Technologies Prithvi N. Rao Carnegie Mellon University Web:
7-1 Digital Serial Input/Output Two basic approaches  Synchronous shared common clock signal all devices synchronised with the shared clock signal data.
ECE 371- Unit 11 Introduction to Serial I/O. TWO MAJOR CLASSES OF SERIAL DATA INTERFACES ASYNCHRONOUS SERIAL I/O - USES “FRAMING BITS” (START BIT AND.
SEQUENTIAL CIRCUITS USING TTL 74XX ICS
Design and Synthesis of Universal Asynchronous Receiver and Transmitter (UART) Using Verilog HDL Prepared by: Engr. Qazi Zia, Assistant Professor EED,
Asynchronous Counter © 2014 Project Lead The Way, Inc.Digital Electronics.
1 SCI Serial Communication Interface Gerrit Becker James McClearen Charlie Hagadorn October 21, 2004.
The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL Keyboard Interface Anselmo Lastra.
Asynchronous Counters with SSI Gates
Selda HeavnerFIELDS iPDR – Antenna Electronics Board Solar Probe Plus FIELDS Instrument PDR Antenna Electronics Board Selda S. Heavner U.C. Berkeley
The 8253 Programmable Interval Timer
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
AT91 Embedded Peripherals
Array Photometer Circuit Design and Interface Tohoku University CDR Meeting, July 2001.
Communication methods
THEMIS Engineering Peer Review 1 UCB, October 15-16, 2003 Electric Field Instrument (EFI) Electrical Fabrication and Test.
Advanced Microprocessor1 I/O Interface Programmable Interval Timer: 8254 Three independent 16-bit programmable counters (timers). Each capable in counting.
Atmel Atmega128 Overview ALU Particulars RISC Architecture 133, Mostly single cycle instructions 2 Address instructions (opcode, Rs, Rd, offset) 32x8 Register.
TRIO-CINEMA 1 UCB, 2/08/2010 Cinema Stein Interface FPGA (CSI) [Part II] Karthik Lakshmanan CINEMA - EE Team Space Sciences Laboratory University of California,
Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.
RBSP Radiation Belt Storm Probes RBSP Radiation Belt Storm Probes 3-4 Sept. 2008EFW INST+SOC PDR217 RBSP Electric Field and Waves Instrument (EFW) Instrument.
1 October 26, 2006ME 6405 MechatronicsSerial Communication Interface Brian Guerriero Jon Rogers Robert Thiets.
Digital Logic Design.
OCRP RF Control WINLAB – Rutgers University Date : June Authors : Prasanthi Maddala, Khanh Le,
MECH1500 Chapter 3.
PS/2 Mouse/Keyboard Port
OCRP RF Control WINLAB – Rutgers University Date : June Authors : Prasanthi Maddala, Khanh Le,
Basic terminology associated with counters Technician Series
The Spartan®-3E FPGA Starter Kit board. A computer mouse is designed mainly to detect two-dimensional motion on a surface. Its internal circuit measures.
THEMIS Instrument PDRGSE- 1 UCB, October 15-16, 2003 IDPU Ground Support Equipment Preliminary Design Review F. Harvey University of California - Berkeley.
FGM peer PDR Magnetsrode - 1 Braunschweig, October 8-9, 2003 MAGNETOMETER CALIBRATION Ingo Richter Institut für Geophysik und Meteorologie TU Braunschweig.
FGM peer CDR GSE - 1 Berlin, April 6, 2004 Ground Support Equipment Concept (GSE) Werner Magnes Institut für Weltraumforschung (IWF) Austrian Academy of.
FGM peer PDR GSE - 1 Braunschweig, October 8-9, 2003 Ground Support Equipment Concept (GSE) Werner Magnes Institut für Weltraumforschung (IWF) Austrian.
FGM peer CDR I/F - 1 Berlin, April 6, 2004 Digital Interface (I/F) Aris Valavanoglou Institut für Weltraumforschung (IWF) Austrian Academy of Sciences.
Rohini Ravichandran Kaushik Narayanan A MINI STEREO DIGITAL AUDIO PROCESSOR (BEHAVIORAL MODEL)
GoetzPre-PDR Peer Review October 2013 FIELDS Time Domain Sampler Peer Review Keith Goetz University of Minnesota 1.
CE-2810 Dr. Mark L. Hornick 1 Serial Communications Sending and receiving data between devices.
THEMIS Instrument PDR 1 UCB, October 15-16, 2003 ESA & SST (ETC) Interface Board Preliminary Design Review Robert Abiad University of California - Berkeley.
IDPU F1 Test Review FGM Fluxgate Magnetometer Michael Ludlam University of California - Berkeley.
Timothy Edward Quinn FIELDS iPDR – GSE Solar Probe Plus FIELDS Instrument PDR GSE Timothy Edward Quinn UCB 1.
The World Leader in High Performance Signal Processing Solutions SD/SDIO Introduction Cliff Cai.
Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.
THEMIS Mission PDR/CAR 1 UCB, November 12-14, 2003 Instrument Design Fluxgate Magnetometer (FGM) Werner Magnes Institut fuer Weltraumforschung (IWF) Austrian.
FGM peer CDR FGE FPGA - 1 Berlin, April 6, 2004 FGE FPGA Olaf Hillenmaier Magson GmbH.
S-band Telemetry Description DMC 211 October 2015.
Generic Remote Interface Unit (RIU) Interface Control Document (ICD)
Serial mode of data transfer
FGM CDR FGM Electronics (FGE) Ronald Kroth MAGSON GmbH Berlin Germany.
INSTRUMENT DATA PROCESSING UNIT (IDPU) REQUIREMENTS
ESA GSE.
Data handling, timing and power distribution scheme
Preliminary Design Review
UQC113S2 – Embedded Systems
Operational Description
FGM S/C Integration Requirements
THEMIS INSTRUMENT TRAINING
E3165 DIGITAL ELECTRONIC SYSTEM
Serial Communication Interface: Using 8251
Sequential Design Example
Serial Communications
Introduction Communication Modes Transmission Modes
Presentation transcript:

FGM peer PDR I/F - 1 Braunschweig, October 8-9, 2003 Digital Interface (I/F) Aris Valavanoglou Institut für Weltraumforschung (IWF) Austrian Academy of Sciences

FGM peer PDR I/F - 2 Braunschweig, October 8-9, 2003 Command & Data Interface Based on THEMIS IDPU backplane specification Serial protocol synchronized to a 2^23 Hz clock (CLK8MHz) FGE receives its own set of CDI signals CLK (continuous signal provided by DCB) –2^23 Hz (CLK8MHz) –1 Hz (CLK1Hz) Command (CMD) FGE returns messages via two telemetry (TLM) signals –TMH (128 Hz vector rate continuously) –TML (4 … 128 Hz per command)

FGM peer PDR I/F - 3 Braunschweig, October 8-9, 2003 Serial Interface Circuit Two clock signals –1 Hz, 2^23 MHz One Command Line Two Telemetry Lines –High Rate (TMH) –Low Rate (TML) TMH with 128 Hz vector rate  DFB, spin fit calculations TML with 4 … 128 Hz vector rate x2: CLK1Hz and CLK8MHz x2: TMH and TML

FGM peer PDR I/F - 4 Braunschweig, October 8-9, bits long Plus Start, Stop and odd Parity bit (calculated without Start bit) FGE clocks in the data bits on the falling edge of CLK8MHz Data transferred MSB first 8-bit identifier in the MSB (FGE CMD_ID = $8x) 16-bit data field in the LSB (CMD_DATA) Wrong commands rejected but not reported to IDPU Synchronization by first non-zero (Start) bit after 25 zeros Command Interface Command I/F Timing

FGM peer PDR I/F - 5 Braunschweig, October 8-9, 2003 Commands First Part of Commands:

FGM peer PDR I/F - 6 Braunschweig, October 8-9, 2003 Commands Second Part of Commands:

FGM peer PDR I/F - 7 Braunschweig, October 8-9, bit long message word Plus Start bit Message preceded by 17 zeros End of message indicated by Zero instead of Start bit again FGE message consists of 3 x 24-bit vectors Each vector sign extended into 2 x 16 bit words FGE message length is 6 x 16 words (X-MSW, X-LSW, Y-MSW …) Same format for TMH and TML Telemetry Interface Telemetry I/F Timing

FGM peer PDR I/F - 8 Braunschweig, October 8-9, 2003 Synchronization Time Synchronization Constant delay between data acquisition and data transmission (derived from 2^23 Hz CLK) Time stamping done by IDPU Start of data acquisition with one second sync (TBD) Clock Timing