HDL Model Combinational circuits. module halfadder(s, cout, a, b); input a, b; output s, cout; xor g1(s, a, b); and g2(cout, a, b); endmodule.

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Presentation transcript:

HDL Model Combinational circuits

module halfadder(s, cout, a, b); input a, b; output s, cout; xor g1(s, a, b); and g2(cout, a, b); endmodule

module fulladder(s, c, x, y, z); input x, y, z; output s, c; halfadder HA1(s1, c1, x, y); halfadder HA2(s, c2, s1, z); or g1(c, c1, c2); endmodule

module ripplecarryadder4bit(S, c4, A, B, c0); output [3:0] S; output c4; input [3:0] A, B; input c0; wire c1, c2, c3; fulladder FA0(S[0], c1, A[0], B[0], c0); fulladder FA1(S[1], c2, A[1], B[1], c1); fulladder FA2(S[2], c3, A[2], B[2], c2); fulladder FA3(S[3], c4, A[3], B[3], c3); endmodule

//HDL Example 3-1 // //Description of the simple circuit of Fig module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y, C); or g3(x,e,y); endmodule

//HDL Example 3-2 // //Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C); endmodule

//Stimulus for simple circuit module stimcrct; reg A,B,C; wire x,y; circuit_with_delay cwd(A,B,C,x,y); initial begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; B = 1'b1; C = 1'b1; #100 $finish; end endmodule //Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C); endmodule

//HDL Example 3-4 // //Circuit specified with Boolean equations module circuit_bln (x,y,A,B,C,D); input A,B,C,D; output x,y; assign x = A | (B & C) | (~B & C); assign y = (~B & C) | (B & ~C & ~D); Endmodule //assign statement describes Boolen equations. AND & OR | ~ negate

//HDL Example 3-5 // //User defined primitive(UDP) primitive crctp (x,A,B,C); output x; input A,B,C; //Truth table for x(A,B,C) = Minterms (0,2,4,6,7) table // A B C : x (Note that this is only a comment) : 1; : 0; : 1; : 0; : 1; : 0; : 1; : 1; endtable endprimitive

//HDL Example 4-2 // //Gate-level hierarchical description of 4-bit adder // Description of half adder (see Fig 4-5b) module halfadder (S,C,x,y); input x,y; output S,C; //Instantiate primitive gates xor (S,x,y); and (C,x,y); endmodule

//Description of full adder (see Fig 4-8) module fulladder (S,C,x,y,z); input x,y,z; output S,C; wire S1,D1,D2; //Outputs of first XOR and two AND gates //Instantiate the halfadder halfadder HA1 (S1,D1,x,y), HA2 (S,D2,S1,z); or g1(C,D2,D1); endmodule

//Description of 4-bit adder (see Fig 4-9) module _4bit_adder (S,C4,A,B,C0); input [3:0] A,B; input C0; output [3:0] S; output C4; wire C1,C2,C3; //Intermediate carries //Instantiate the fulladder fulladder FA0 (S[0],C1,A[0],B[0],C0), FA1 (S[1],C2,A[1],B[1],C1), FA2 (S[2],C3,A[2],B[2],C2), FA3 (S[3],C4,A[3],B[3],C3); endmodule

//HDL Example 4-5 // //Dataflow description of a 4-bit comparator. module magcomp (A,B,ALTB,AGTB,AEQB); input [3:0] A,B; output ALTB,AGTB,AEQB; assign ALTB = (A < B), AGTB = (A > B), AEQB = (A == B); endmodule

//HDL Example 4-6 // //Dataflow description of 2-to-1-line multiplexer module mux2x1_df (A,B,select,OUT); input A,B,select; output OUT; assign OUT = select ? A : B; Endmodule // if select =1 then OUT = A, else OUT =B

//HDL Example 4-3 // //Dataflow description of a 2-to-4-line decoder //See Fig.4-19 module decoder_df (A,B,E,D); input A,B,E; output [0:3] D; assign D[0] = ~(~A & ~B & ~E), D[1] = ~(~A & B & ~E), D[2] = ~(A & ~B & ~E), D[3] = ~(A & B & ~E); endmodule

//HDL Example 4-4 // //Dataflow description of 4-bit adder module binary_adder (A,B,Cin,SUM,Cout); input [3:0] A,B; input Cin; output [3:0] SUM; output Cout; assign {Cout,SUM} = A + B + Cin; endmodule

//HDL Example 4-7 // //Behavioral description of 2-to-1-line multiplexer module mux2x1_bh(A,B,select,OUT); input A,B,select; output OUT; reg OUT; (select or A or B) if (select == 1) OUT = A; else OUT = B; endmodule

//HDL Example 4-8 // //Behavioral description of 4-to-1- line multiplexer //Describes the function table of Fig (b). module mux4x1_bh (i0,i1,i2,i3,select,y); input i0,i1,i2,i3; input [1:0] select; output y; reg y; (i0 or i1 or i2 or i3 or select) case (select) 2'b00: y = i0; 2'b01: y = i1; 2'b10: y = i2; 2'b11: y = i3; endcase endmodule