In AMIS CMOS 07 by Roman Prokop

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Presentation transcript:

In AMIS CMOS 07 by Roman Prokop Current mirror design In AMIS CMOS 07 by Roman Prokop

Simple current mirror Saturace

AMIS CMOS 07 param VT0 & KP = f (T, process) graphs NMOS Process VT0 [V] Kp [A/V2] Temp [°C] Typ 0.75 9. 10-5 27 Fast 0.7 1.75 .10-4 -50 0.45 7 .10-5 150 Slow 1.00 1.25 .10-4 5 .10-5

W/L calculation for typ parameters Choose ∆VGS= 250 mV & ID= 20 μA

Ideal Vds1=Vds2 solution - Decrease the Vds influence  large L - cascoda

min. ∆VGS max. ∆VGS Then input current can vary between (even for fix (dummy) resistor R) 150°C hipo(min)IIN ↑ -50°C hipo(max)IIN ↓

How to get fixed voltage for current mirror biasing ?

How to get fixed voltage for current mirror biasing ? better – doesn’t depend on Ucc

Matching hand calculation Premise - 2 transistors in common centroid (crossquad) - ideal surrounding Instructions in: “Electrical parameters CMOS07” manual (ds13291.pdf) A1 A2 B1 B2 Exemplary calculation – choose W/L=7  W/L= 35u/5u quite small MOS

Matching Error in VT0 Error in β Statistical errors – - count under square root For good matching (small current difference) - larger MOS  high WL - higher (VGS – VT0)

Matching Table is valid for NMOS, PMOS parameters in electrical parameters Carefully: units mV, μm, %

Matching

Matching Cadence matching tool output file

Biasing currents Usually use buffered band-gap reference voltage 1 - External resistor - accurate resistance value, almost temperature independent 2 – Hipo internal resistor - hipo resistance 2000 Ω (1600 Ω - 2400 Ω) - temperature dependence - viz. parameterFile 3 – other CMOS resistor types - not used because of small sheet resistance One chip can combine both types of bias currents

Biasing currents Hipo internal resistor bias current advantages - temperature dependent current can help with stability of some circuits - quite accurate voltage level shifter Current mirror and resistor MATCHING !!!!

Cascoded mirror output resistance express It negligible

Good luck !!!