Lecture 17 Final Review Prof. Mike Schulte Computer Architecture ECE 201

Final Format 3 hour exam. 4:00 to 7:00 PM in PL101 on 5/10/01. Open book, open note 20% on chapters 1-4, 80% on chapters 5-7 –stuff from chapters 1-4 in context of chapters problems with multiple parts Similar in format to the midterm and the practice final

Things to Review Homeworks assignments, especially 3-5 Lecture notes, especially 8 to 16 Book, especially chapters 5-7 Sample final and practice final Your own notes The project

Chapter 5: Processor Design Know elemenents used for datapath design –registers, register file, memory, multiplexors, adders, ALUs, etc. Single cycle and multicycle implementations –Construct a datapath and control for a specific set of instructions –Modify the datapath and control to add instructions –Knowing what parts of the datapath are active for various instructions –Single cycle vs. multicycle processor design »how do they differ? –Determining and comparing performance –Exceptions and exception handling

Chapter 6: Pipelining Basic pipeline performance and effects of hazards on performance Pipelined version of the MIPS processor How does pipelined processor design differ from multiple cycle processor design? Pipeline harzards –Structural hazards –Data hazards –Control hazards –Drawing pipeline diagrams to identify hazards and stalls add $5, $7, $1 add $6, $3, $5, sw $6, 200($0)

Chapter 6: Pipelining Dealing with hazards –Pipeline stalls –Forwarding –Duplication of resources –Branch prediction –Delayed branches –Reordering instructions –Loop unrolling Superscalar and superpiplining in MIPS What are the advantages and disadvantages of superscalar and superpipelining? What are the effects of increasing the pipeline depth?

Chapter 7: Memory Hierarchy Temporal and spatial locality - examples Concepts of memory hierarchies –Memory close to the processor is faster, smaller, and more expensive –Take advantage of locality Basics of caches –How to access a cache, hit or miss –Determining the size of the byte offset, index, and tags –Determining total number of bits in the cache –Drawing diagrams of different types of caches Improving cache performance –Increasing the size of the cache –Increasing the block size –Increasing associativity –Adding a second level cache

Chapter 7: Memory Hierarchy The four Q's of memory hierarchies –Where can a block be placed? –How is a block found? –Which block should be replaced on a miss? (LRU vs. Random) –What happens on a write? (write thorugh vs. write back) The three C's of memory misses –Compulsory misses : first access to a block –Capacity misses : cache cannot contain all the blocks –Conflict misses : due to limited associativity Memory performance and determining the average memory access time

Chapter 7: Memory Hierarchies Virtual Memory –Benefits of virtual memory – Address tranlation processes: virtual address -> physical address –Page tables –Translation lookaside buffers –Handling page faults –Virtually vs. physcially addressed caches