Improvement of ULTIMATE IPHC-LBNL September 2011 meeting, Strasbourg Outline  Summary of Ultimate test status  Improvement weak points in design

STAR IPHC 2 5-6/09/2011 Meeting LBNL/IPHC Main Characteristics of ULTIMATE 0.35 μm process with high-resistivity epitaxial layer Column // architecture with in-pixel cDS & amplification End-of-column discrimination and binary charge encoding, followed by Ø Active area: 960 columns of 928 pixels (19.9×19.2 mm 2 ) Pitch: 20.7 μm  ~0.9 million pixels  Charge sharing   sp ~> 3.5 μm expected t r.o. < 200 μs ( ~5×10 3 frames/s)  suited to >10 6 part./cm 2 /s 2 outputs at 160 MHz <~150 mW/cm2 power consumption

STAR IPHC 3 5-6/09/2011 Meeting LBNL/IPHC Ultimate: Performances Summary Test in Lab:  N <~15 e - ENC at 30-35°C (as MIMOSA-22AHR)  CCE (55Fe) similar to MIMOSA-22AHR M.I.P. Detection Performances:  Beam tests at CERN-SPS with O(10 2 ) GeV ”  - beam”  test variables (preliminary results) : Operating temperature : 20 & 30°C Ionising radiation dose : 0 & 150 kRad Steering voltage : 3.3 & 3.0 V  Detection efficiency closed to 100%  Single point resolution better than 4 µm  Average fake rate ratio << 10 -4

STAR IPHC 4 5-6/09/2011 Meeting LBNL/IPHC Ultimate: Analogue Output Analogue signal cannot be read out at nominal frequency due to large CDS offset  Problem identified: Coupling between the bias of the output buffer & READ signal in the layout Marker (MKA) despaired at 160 MHz (156 MHz is ok)  Problem not identified READ periodCALIB period Analogue Output

STAR IPHC 5 5-6/09/2011 Meeting LBNL/IPHC Ultimate: Offset dispersion Offset is frequency, temperature and steering voltage (VddD) sensible

STAR IPHC 6 5-6/09/2011 Meeting LBNL/IPHC Ultimate: Offset dispersion (2) Column level distribution:  Large offset in every 16 rows: understood Structure in the design  reduce C col Slct_Gr = 16 x Slct_Row No sufficient setting time for the 1st row of every group Propose of modification  make Slct_Gr signal less sensible  "half moon" phenomenon is still investigating Improve setting time during "READ" phase  Optimisation Slct_Row MOS in pixel (both in column & row levels) Check Slct_Row, Clp row by row distribution Red curve proposed for modification

STAR IPHC 7 5-6/09/2011 Meeting LBNL/IPHC Ultimate: Offset dispersion (3) Row level distribution:  RC distribution of digital control signals per row: Slct_Row, (CLP)  Slct_Row delay can reach to a few ns along a row of 2 cm long Pixel output hasn't enough Offset dispersion of (READ-CALIB) can reach Slct_Row Analog Output of a pixel row READ CALIB  Improve setting time during "READ" phase  Optimisation Slct_Row MOS in pixel (both in column & row levels)

STAR IPHC 8 5-6/09/2011 Meeting LBNL/IPHC Ultimate: Yield of "V-clamping Regulator" Ref. Claude Status:  Among 13 bonded ULTIMATE, 4 have a non-working internal VCLP regulator  VCLP pad voltage about 0.3/0.4V in place of the expected ~2.1V  VCLP can be supplied via an external regulator and the chip becomes functional  Both internal & external VCLP have been successfully operated during beam tests Possible causes of the regulator failure:  Regulator itself: architecture / layout implementation  Weak short in the matrix may overload the regulator because no current is expected to by driven Clp Vdd! V_clp M8 M9 M10 VCLP PAD Internal Regulator V=2.1 V I ~0 Pixel Array Enable & disable by JTAG External Regulator

STAR IPHC 9 5-6/09/2011 Meeting LBNL/IPHC Ultimate: Yield of "V-clamping Regulator" (2) Diagnostic:  Current provided by the external VCLP shows: ~400nA for the 9 good chips and ~3mA for the 4 bad (disable VCLP regulator via JTAG)  All 4 bad chips have dead pixels!!!  Non-working VCLP v.s. Dead pixels? Why dead pixels:  During process manufacture?  Manipulation in lab? (Historical reason) VCLP Pad is a non ESD protected pad (as Mimosa26) Actions;  Get more statistic values by testing MIMOSA26 or ULTIMATE chips  Using ESD pad in a next fabrication Improve/suppress dead rows/columns of pixels ?  Design a new regulator which can provide more current!