Paulo Moreira On behalf of the GBT collaboration 2015 – 02 – 23 The LpGBT Project Paulo Moreira On behalf of the GBT collaboration 2015 – 02 – 23 http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

Outline GBT Project News LpGBT & VL+ Link Architecture The Low power GBTX (LpGBTX) Achieving low lower operation Link bandwidth Downlink Uplink – FEC 5 Uplink – FEC 12 Slow control functionality LpGBT project developments GBLD10 LpGBLD LpGBTX http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

GBT Project News The GBT chipset comprises: GBTIA: 4.8 Gb/s Transimpedance Amplifier Amplifies the weak photo-current detected by the PIN diode GBLD: 4.8 Gb/s Laser Driver Modulates laser current to achieve electro-optical conversion GBTX: 4.8 Gb/s Transceiver Manages the communications between the counting room and the frontend modules GBT – SCA Slow Control Adapter Experiment control and environment monitoring All the chips have now been prototyped: GBTIA, GBLD and GBTX: Have been successfully prototyped Radiation tolerance proved to > 100 Mrad GBT – SCA: First test results are very encouraging: Digital: functionality good Analogue: first results are good: Exhaustive characterization still being done. Radiation qualification to be done Production of the chipset will take place during 2015 GBTIA GBLD GBT – SCA GBTX http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

LpGBT & VL+ Link Architecture High radiation doses No or small radiation doses LHC: up to 100 Mrad (1014 1MeV n/cm2) HL – LHC: up to 1 Grad (1016 1MeV n/cm2) On-Detector Radiation Hard Electronics Off-Detector Commercial Off-The-Shelf (COTS) LpGBTX GBTIA GBLD PD LD Custom ASICs Timing & Trigger DAQ Slow Control FPGA LpGBT GBT Versatile Link Electrical links to the frontend modules. Lengths: cm to few m Short distance optical links: 100 to 300 m Same “philosophy”: radiation hard components in the detectors and COTS in the counting room ECFA 2014 Paulo.Moreira@cern.ch

The Low Power GBTX (LpGBTX) Low Power Dissipation and Small Footprint: Target: 500 mW (GBTX: 2W) Critical for pixel detectors Critical for tracker/triggering detectors Bandwidth: Low-Power mode 2.56 Gb/s for the optical down link 5.12 Gb/s for the optical up link High-Speed mode: 10.24 Gb/s for the optical up link e-Links: Down-links: 80, 160 and 320 Mb/s Up-Links, Low-Power Mode: 160, 320 and 640 Mb/s Up-Links, High-Speed Mode: 320, 640 and 1280 Mb/s Functionality: “Replica” of the GBTX Reduced subset of the GBT Slow Control Adapter (GBT – SCA) functionality will be included ECFA 2014 Paulo.Moreira@cern.ch

Achieving Low Power Operation Technology 130 nm → 65 nm Vdd: 1.5 V → 1.2 V Architecture Serializer / CDR circuits “merged” Rationalization of the clock frequencies: Single PLL will be used to generate all the clock frequencies needed PLL shared by all the functional blocks Binary counter generates all the required frequencies: 5.12 GHz down to 80 MHz (all with 50% duty cycle) Transmit and receive frequencies are binary multiples of 40 MHz: Down-link frame: 64 – bits (× 40 MHz) Up-link frame: 128 or 256 – bits (× 40 MHz) FPGA vendors documentation supports the use of these frame sizes: Examples are: Xilinx: Family 7 Altera: Family V and 10 Achronix: Speedster22iHD Successful LAB demo made with XILINX Virtex7 http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

Preliminary Downlink Single data rate: Frame: Error correction: 2.56 Gb/s Frame: Data field: 32 – bit 1.28 Gb/s EC field: 2 – bit 80 Mb/s IC field: FEC field: 24 – bit Error correction: FEC: Interleaving: 4 Symbol width: 3 – bit Number of wrong symbols: 1 ( × 4) Up to 12 consecutive bits Efficiency: 56% eLinks: Data 16 eLinks @ 80 Mb/s 8 eLinks @ 160 Mb/s 4 eLinks @ 320 Mb/s EC 1 eLink @ 80 Mb/s Option   37 Frame (bits) 64 Header (bits) 4 Coded header Yes User field (bits) 36 Code (bits) 24 8-bit multiplicity 4.5 User Bandwidth (GHz) 1.44 # eLinks groups (8 bit) eLinks bandwidth (MHz) 80/160/320 #eLinks 16/8/4 EC bandwidth (MHz) 80 IC bandwidth (MHz) Corrected (bits) 12 Efficiency 56% Preliminary http://cern.ch/proj-gbt LpGBTX Block Diagrams

Uplink – FEC 5 (Target: Bandwidth) Dual data rate: 5.12 Gb/s 10.24 Gb/s Frame: Data field: 112 / 224 – bit 4.48 / 8.96 Gb/s EC field: 0 / 2 – bit 0 / 80 Mb/s IC field: 2 / 2 – bit 80 / 80 Mb/s FEC field: 10 / 20 – bit Error correction: FEC: Interleaving: 1 / 2 Symbol width: 5 – bit Number of wrong symbols: 1 ( × 1 / × 2) Up to 5 / 10 consecutive bits Efficiency: 89% eLinks: Data 28 eLinks @ 160 / 320 Mb/s 14 eLinks @ 320 / 640 Mb/s 7 eLinks @ 640 / 1280 Mb/s EC 1 eLink @ 80 / 160 Mb/s Bit rate 5.12 Gb/s 10.24 Gb/s Option   7 Frame (bits) 128 2 x 128 Header (bits) 4 Coded header Yes User field (bits) 114 228 Code (bits) 10 20 16-bit multiplicity 7.125 14.25 User Bandwidth (GHz) 4.56 9.13 # eLinks groups (16 bit) eLinks bandwidth (MHz) 160/320/640 320/640/1280 #eLinks 28/14/7 EC bandwidth (MHz) 80 IC bandwidth (MHz) Corrected (bits) 5 2 x 5 Efficiency 89% Preliminary http://cern.ch/proj-gbt LpGBTX Block Diagrams

Uplink – FEC 12 (Target: SEU Tolerance) Dual data rate: 5.12 Gb/s 10.24 Gb/s Frame: Data field: 96 / 192 – bit 3.84 / 7.68 Gb/s EC field: 2 / 4 – bit 80 / 160 Mb/s IC field: 2 / 2 – bit 80 / 80 Mb/s FEC field: 24 / 48 – bit Error correction: FEC: Interleaving: 3 / 6 Symbol width: 4 – bit Number of wrong symbols: 1 ( × 3 / × 6) Up to 12 / 24 consecutive bits Efficiency: 78% eLinks: Data 24 eLinks @ 160 / 320 Mb/s 12 eLinks @ 320 / 640 Mb/s 6 eLinks @ 640 / 1280 Mb/s EC 1 eLink @ 80 / 160 Mb/s Bit rate 5.12 Gb/s 10.24 Gb/s Option   28 Frame (bits) 128 2 x 128 Header (bits) 4 Coded header Yes User field (bits) 100 200 Code (bits) 24 48 16-bit multiplicity 6.25 12.5 User Bandwidth (GHz) 8 # eLinks groups (16 bit) 6 eLinks bandwidth (MHz) 160/320/640 320/640/1280 #eLinks 24/12/6 EC bandwidth (MHz) 80 80/160 IC bandwidth (MHz) Corrected (bits) 12 2 x 12 Efficiency 78% Preliminary http://cern.ch/proj-gbt LpGBTX Block Diagrams

Preliminary “SC” Functionality Slow Control Functionality Three I2C masters: One dedicated to the Versatile Link 8 - bit ADC: 4 inputs Temperature: On chip: yes Sensor: yes Voltage monitoring DC/DC input voltage 8 x DIO (programmable parallel port) Preliminary http://cern.ch/proj-gbt LpGBTX Block Diagrams

LpGBT development: GBLD10 Prototype: A low-power 10 Gb/s laser driver was prototyped in 130 nm CMOS Main Features: VCSEL driver Minimum bit rate : 10 Gb/s Programable pre-emphasis Modulation current: 0 – 12 mA Distributed amplifier structure QFN package, and ESD protection Area: 2mm x 2mm (same as GLBD) Measurement results: Data rate: > 10 Gb/s Power dissipation: 86 mW (typical settings) Jitter: < 20 ps Input Return Loss: < -14 dB (0 – 5 GHz) < -3 dB (10 GHz – 20 GHz) Radiation hardness proved up to 200 Mrad Electrical Eye Diagram @ 10 Gb/s See: Zhang et all, TWEPP 2014 ECFA 2014 Paulo.Moreira@cern.ch

New Developments LpGBLD 10 Gb/s laser driver Very low power consumption: < 70 mW Including VCSEL bias and modulation currents Falling edge pre-emphasis Directly bonded to the VCSEL Single ended output Merged modulation and bias currents Compatible with the VL+ project (See Jan Troska’s presentation): Size: 1.9 mm × 0.4 mm Supply: 1.2 and 2.5 V Technology: 65 nm CMOS Prototyping May 2015 Collaboration SMU / KU LEUVEN / CERN http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

New Developments LpGBTX Specification work undergoing Will be released for discussion and approval with the experiments Architecture definition Phase-aligners definition and detailed design Schedule March/April 2015: Approval of the specifications January 2016: Package design June 2016: Fabrication of the test systems December 2016: Prototyping of the full chip April 2017: Packaging July 2017 Prototype testing December 2017 TID and SEU testing April 2018 Engineering run Preparation of the production tests Collaboration CERN / SMU / KU LEUVEN http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

Backup Slides on the GBT Project http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

Available Quantities and Status GBTIA: Chips/wafer: 2144 4 wafers (8576 chips) Chips will be wafer probed at CPPM GBLD: Chips/wafer: 1340 3 wafers (4020 chips) wafers shared with GBT – SCA 2650 parts packaged by NovaPack A small sample already tested GBTX: Chips/wafer: 536 4 wafers (2136 chips) 180 parts packaged by ASE All packaged parts tested (yield 97.8%) GBT – SCA Chips/wafer: 268 3 wafers (804 chips) wafers shared with GBLD 208 parts packaged by NovaPack First test results are very encouraging http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

ASICs Production Production wafers: Quantities: Lead time 4 months Earliest availability: June/July 2015 Still to be ordered Quantities: GBTX: ~60k GBLD: ~60k GBTIA: ~15k GBT – SCA: ~15k (GBTX) Crystal production: Pre-production: March 2015 (contract + 6 weeks) Production follows in batches of 15k Complete October 2015 (contract + 34 weeks) GBTX packaging: To start June/July GBLD packaging: Start June/July 2015 GBTIA: Integrated in the VTRX (See Jan’s presentation) Cost for the User GBTX 50 CHF GBT-SCA 24 CHF VTRX (MM) 200 CHF VTTX (MM) 150 CHF http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

GBT Chipset & VL Components Quantities (6 Feb. 2015)   TOSA ROSA Latch VTRx VTTx GBTX GBT-SCA GBLD GBTIA User SM MM LHCb 16000 2000 9000 7000 14000 6000 CMS HCAL 200 5690 270 2980 2710 1300 5890 470 CMS GEM 2930 ATLAS SmallWh 3500 1200 2350 1150 2300 ATLAS SmallWh option ATLAS LArg 600 ATLAS LArg Option 3000 ALICE 10000 3600 6800 3200 5000 BE-BI-BL 500 BE-BI-QP BE-CO-FE CBM@FAIR 6700 2500 4600 2100 PANDA@FAIR 220 Total 45420 13100 29330 13320 16160 38550 13500 52620 14300 Option 7200 Total with option 51420 32330 19160 45750 58620 http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

Backup Slides on the LpGBT http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

Error Cross Section and Data Rate http://cern.ch/proj-gbt Paulo.Moreira@cern.ch

DEC & ePortTx DSCR SerDes Phase Shifter Control SCA SCR ePortRx ENC 5.12 / 10.24 Gb/s 2.56 Gb/s refClk40MHz cdrOut [63:0] serIn [255:0] DEC & DSCR rxData[31:0] SCR ENC rxEc[1:0] ePortTx eLinkOut[15:0] ecOut ePortRx eLinkIn[27:0] ecIn 40/…/1280 MHz 40 MHz SCA (Reduced set) txData[159:0] txEc[3:0] Phase Shifter eClock[27:0] LpGBTX Control SerDes 40 / 80 / 160 / 320 / 640 /1280 MHz rxIc[1:0] txIc[1:0] 40/…/320 MHz cnt[x:0] psClk[3:0] I2C (x3) adcIn[3:0] pio[7:0] analog data control clock http://cern.ch/proj-gbt LpGBTX Block Diagrams