Attacking the Power-Wall by Using Near-threshold Cores Liang Wang

Power Wall The end of Classical Scaling. – Vdd: almost constant – Power density: roughly increase in exponential – Utilization: roughly decrease in exponential We can fabricate more cores than we can power up * From Venkatesh, et. al. ASPLOS’10 Dark Silicon 2Liang Wang, ECE6332 Final

Near-threshold Cores (NVt. Cores) Pros – Low power per-core. – More cores per-chip. Limitations – Low per-core frequency, reducing throughput gains from parallelization. – Variations, harmful for performance and functionality. Will NVt. cores be a viable solution to push down the power-wall? 3Liang Wang, ECE6332 Final

Outline Performance Model Analyses and Results Conclusion 4Liang Wang, ECE6332 Final

System Modeling 5Liang Wang, ECE6332 Final Core Area: A Power: P Area: A Power: P Symmetric Multi-core System Number of active cores Amdahl’s Law Application with parallel ration of  A Single core v Area: a Power: p(v) Freq: f(v) Area: a Power: p(v) Freq: f(v) Dynamic Power Static Power Frequency Fitted to circuit sim.

Simulation Setup Circuit – A single inverter – Ripple carry Adder (32bits, 16bits, 8bits, and 4bits) Technology Library – A modified version of Predictive Technology Model (PTM) Technology Nodes – 45nm, 32nm, 22nm, 16nm Process Variants – HKMGS: High-performance High-K Metal Gate and Stress effect. – LP: Low-power process CAD Tools – RC Compiler – Spectre driven by Ocean Liang Wang, ECE6332 Final6

Voltage-Frequency Scaling 7Liang Wang, ECE6332 Final ~8x ~400x ~15x ~10 3 x LP has much larger frequency drop-down comparing to HP with the same change in vdd 16nm has larger frequency drop-down comparing to 45nm With the same change in vdd

Design space exploration (Area) Liang Wang, ECE6332 Final8 45nm, HKMGS, IO cores, 100w,  =0.99 saturating Peak is capped by total area 2x Peak from 200 to 6.4K

Liang Wang, ECE6332 Final9 Cross-technology study 500mm 2 80W 500mm 2 80W 400mm 2 100W 400mm 2 100W

Compare to Dark Silicon Liang Wang, ECE6332 Final10 NVt. cores alleviate the issue of low utilization. NVt. cores has better performance. (up to 2x) 500mm 2 80W HKMGS 500mm 2 80W HKMGS Available cores on-chip

Variation NVt. cores are very sensitive to variations – Functionality. (ratioed circuits) – Performance. (focused in this project) Monte-Carlo simulation – Performed on every VDD setups – 100 iterations per VDD – Process and mismatch Liang Wang, ECE6332 Final11

Voltage-Frequency Scaling Revisited Liang Wang, ECE6332 Final12 HKMGS – Up to 5x slow down LP – Up to 10x slow down HKMGS – Up to 10x slow down LP – Up to 100x slow down

Impact of Variation 13Liang Wang, ECE6332 Final 400mm 2, 100W, IO Lower Utilization Worse Perf. Flatten Vdd

Conclusion In terms of performance – Simple core (IO) is better. – HP process (HKMGS) is better. Lowering VDD reduces dark silicon, improves throughput. Vulnerable to process variation. 14Liang Wang, ECE6332 Final