Chapter 5 Computer Systems Organization

Levels of Abstraction – Figure 5.1e The Concept of Abstraction

Levels of Abstraction – Figure 5.1b The Concept of Abstraction (Continued)

Levels of Abstraction – Figure 5.1c The Concept of Abstraction (Continued)

Levels of Abstraction – Figure 5.1d The Concept of abstraction (Continued)

Levels of Abstraction – The Hierarchy of Abstraction

Figure 5.2 The Von Neumann Architecture

Memory and Cache – Figure 5.3 Structure of Random Access Memory

Memory and Cache – Figure 5.5 Organization of Memory and Decoding Logic

The Von Neumann Architecture - Figure Two- Dimensional Memory Organization

The Von Neumann Architecture – Figure 5.7 Overall RAM Organization

Memory and Cache – The Organization of the “two- level memory hierarchy” is the above

Input/Output and Mass Storage – A Disk Stores Information in Units called “sectors” Each of Which Contains an Address and a Data Block

Input/Output and Mass Storage – A Fixed Number of Sectors on the Surface of a Disk are Called a Track

Input/Output and Mass Storage – Figure 5.8 Overall Organization of a Typical Disk

Practice Problem – Figure 5.9 Organization of the 1/0 Controller

The Arithmetic/Logic Unit – Figure 5.10 Three-Register ALU Organization

The Arithmetic/Logic Unit – Figure 5.11 Multiregister ALU Organization

The Arithmetic/Logic Unit – Figure 5.12 Using a Multiplexor Circuit to Select the Proper ALU Result

The Arithmetic/Logic Unit Figure 5.13 Overall ALU Organization

The Control Unit – Figure 5.14 Typical Machine Language Format

The Control Unit – The Address Fields

Machine Language Instructions – Figure 5.15 Examples of Simple Machine Language Instruction Sequence

Control Unit Registers and Circuits – Figure 5.16 Organization of the Control Unit Registers and Circuits

Control Unit Registers and Circuits – Figure 5.17 The Instruction Decoder

Putting All The Pieces Together – Figure 5.18 The Organization of a Von Neumann Computer

Figure 5.25 Graph of Computer Speeds 1945 to the Present

The Future: Non-Von Neumann Architectures – Figure 5.26 A SIMD Parallel Processing System

The Future: Non-Von Neumann Architectures – Figure 5.27 Model of MIMD Parallel Processing