Migration to PPC at JLab Richard Dickson. VME data interface differences: 68060 CPU VMEchip2 VME mvme177 System Local Bus PPC 750 CPU Raven VME mvme2700.

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Presentation transcript:

Migration to PPC at JLab Richard Dickson

VME data interface differences: CPU VMEchip2 VME mvme177 System Local Bus PPC 750 CPU Raven VME mvme2700 System Local Bus PCI Bus Universe 1.The completely different bridge chips’ register set resulted in low level VME Direct Memory Access (DMA) code having to be rewritten. 2.Any hard coded system local bus mapped VME addresses fail on this migration since PPC VxWorks maps VME blocks to different space.

VME interrupt differences: 1.Only even VME interrupt vectors allowed. 2.VME interrupt does not preempt ongoing DMA. 3.“Bad VME interrupt 0” messages on console. movestop_irq_value, EOI_reg; write does not complete before rfi; return from interrupt In this case the code execution can erroneously exit interrupt context prior to the IRQ being de-asserted. This was fixed partially by executing an “Enforce In-order Execution of IO (eieio)” instruction prior to the rfi. DMA transfer IRQ ISR Time

Other Problems: 1.VxWorks for the mv2700 configures the PowerPC floating point unit to issue an exception on divide by zero faults (causing task suspension). This was not the case for the 162, 167, 177. The VxWorks taskSpawn command was overloaded to issue a call to this assembly language code to disable FP exceptions on behalf of the task being spawned. 2.In pursuit of increased performance, the PowerPC CPU will combine two consecutive sequential 16 bit writes into a single 32 bit write (referred to as Store Gathering). 16 Bit address address Bit address

Other Problems (cont.): 3.Non-volatile RAM used for maintaining IOC reboot/save/restore dates is not directly accessible (memory mapped) as is the case for a 162, 167, 177 board. Custom driver code was written to emulate this functionality on the A custom, low level code package (known as timevt) existed to provide asynchronous short period timer functionality. This utilized 162/167/177 specific hardware timer architecture that is unavailable on the 2700 platform. 5.The CAMAC interface driver did not work. 6.Serial applications need to be tested. 7.cmlog had problems building.