Simulated Evolution Algorithm for Multi- Objective VLSI Netlist Bi-Partitioning Sadiq M. Sait, Aiman El-Maleh, Raslan Al Abaji King Fahd University of.

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Presentation transcript:

Simulated Evolution Algorithm for Multi- Objective VLSI Netlist Bi-Partitioning Sadiq M. Sait, Aiman El-Maleh, Raslan Al Abaji King Fahd University of Petroleum & Minerals Dhahran, Saudi Arabia 27 th May, ISCAS-2003, Bangkok, Thailand

2  Introduction  Problem Formulation  Cost Functions  Proposed Approaches  Experimental results  Conclusion Outline

3 Design Characteristics 0.13M 12MHz 1.5um CAE Systems, Silicon compilation 7.5M 333MHz 0.25um Cycle-based simulation, Formal Verification 3.3M 200MHz 0.6um Top-Down Design, Emulation 1.2M 50MHz 0.8um HDLs, Synthesis 0.06M 2MHz 6um SPICE Simulation Key CAD Capabilities The challenges to sustain such a fast growth to achieve giga-scale integration have shifted in a large degree, from the process of manufacturing technologies to the design technology. VLSI Technology Trends

4 Technology0.1 um Transistors200 M Logic gates40 M Size520 mm 2 Clock GHz Chip I/O’s4,000 Wiring levels Voltage Power160 Watts Supply current~160 Amps Performance Power consumption Noise immunity Area Cost Time-to-market Tradeoffs!!! The VLSI Chip in 2006

5 1.System Specification 2.Functional Design 3.Logic Design 4.Circuit Design 5.Physical Design 6.Design Verification 7.Fabrication 8.Packaging Testing and Debugging VLSI design process is carried out at a number of levels. VLSI Design Cycle

6 Physical design converts a circuit description (behavioral/structural), into a geometric description. This description is used to manufacture a chip. The physical design cycle consists of: 1.Partitioning 2.Floorplanning and Placement 3.Routing 4.Compaction Physical Design

7  Decomposition of a complex system into smaller subsystems.  Each subsystem can be designed independently speeding up the design process (divide-and conquer- approach).  Dividing a complex IC into a number of functional blocks, each of them designed by one or a team of engineers.  The partitioning scheme has to minimize the interconnections between subsystems. Why do we need Partitioning ?

8 System Level Partitioning Board Level Partitioning Chip Level Partitioning System PCBs Chips Subcircuits / Blocks Levels of Partitioning

9 Partitioning Algorithms Group MigrationIterative Heuristics Performance Driven 1.Kernighan-Lin 2.Fiduccia- Mattheyeses (FM) 3.Multilevel K- way Partitioning Others 1.Simulated annealing 2.Simulated evolution 3.Tabu Search 4.Genetic 1.Lawler et al. 2.Vaishnav 3.Choi et al. 4.Jun’ichiro et al. 1.Spectral 2.Multilevel Spectral Classification of Partitioning Algorithms

10 Related previous Works 1999Two low power oriented techniques based on simulated annealing (SA) algorithm by choi et al. 1969A bottom-up approach for delay optimization (clustering) was proposed by Lawler et al. 1998A circuit partitioning algorithm under path delay constraint is proposed by jun’ichiro et al. The proposed algorithm consists of the clustering and iterative improvement phases. 1999Enumerative partitioning algorithm targeting low power is proposed in Vaishnav et al. Enumerates alternate partitioning and selects a partitioning that has the same delay but less power dissipation. (not feasible for huge circuits.)

11 Need for Power optimization  Portable devices  Power consumption is a hindrance in further integration  Increasing clock frequency Need for delay optimization  In current sub micron design wire delay tend to dominate gate delay.  Larger die size imply long on-chip global routes, which affect performance  Optimizing delay due to off-chip capacitance Motivation

12 Objective Design a class of iterative algorithms for VLSI multi-objective partitioning. Explore partitioning from a wider angle and consider circuit delay, power dissipation and interconnect in the same time, under a given balance constraint Objectives  Power cost is optimized  Delay cost is optimized  Cutset cost is optimized Constraint  Balanced partitions to a certain tolerance degree (10%)

13 Problem formulation The circuit is modeled as a hypergraph H(V,E), where V ={v 1,v 2,v 3,… v n } is a set of modules (cells). And E = {e 1, e 2, e 3,… e k } is a set of hyperedges. Being the set of signal nets, each net is a subset of V containing the modules that the net connects. A two-way partitioning of a set of nodes V is to determine two subsets V A and V B such that V A U V B = V and V A  V B = 

14  Based on hypergraph model H = (V, E)  Cost 1: c(e) = 1 if e spans more than 1 block  Cutset = sum of hyperedge costs  Efficient gain computation and update cutset = 3 Cutset

15 path  : SE 1  C 1  C 4  C 5  SE 2. Delay  = CD SE1 + CD C1 + CD C4 + CD C5 + CD SE2 CD C1 = BD C1 + LF C1 * ( Coffchip + CINP C2 + CINP C3 + CINP C4 ) Delay Model

16 The average dynamic power consumed by CMOS logic gate in a synchronous circuit is given by: Ni is the number of output gate transition per cycle (Switching Probability) load capacitance = Load Capacitances before Partitioning + load due to off chip capacitance Power Total Power dissipation of a Circuit:

17 Weighted Sum Approach 1.Problems in choosing weights. 2.Need to tune for every circuit. Unifying Objectives by Fuzzy logic  Imprecise values of the objectives  best represented by linguistic terms that are basis of fuzzy algebra  Conflicting objectives  Operators for aggregating function

18 1.The cost to membership mapping 2.Linguistic fuzzy rule for combining the membership values in an aggregating function 3.Translation of the linguistic rule in form of appropriate fuzzy operators 4.And-like operators: Min operator  = min (  1,  2) And-like OWA:  =  * min (  1,  2) + ½ (1-  ) (  1+  2) Or-like operators Max operator  = max (  1,  2) Or-like OWA:  =  * max (  1,  2) + ½ (1-  ) (  1+  2) Where  is a constant in range [0,1] Fuzzy logic for Multi-objective function

19 WhereO i and C i are lower bound and actual cost of objective “i”  i (x) is the membership of solution x in set “good ‘i’ ” g i is the relative acceptance limit for each objective. Membership functions

20 A good partitioning can be described by the following fuzzy rule IF solution has small cutset AND low power AND short delay AND good Balance. THEN it is a good solution Fuzzy linguistic rule

21 The above rule is translated to AND-like OWA Represent the total Fuzzy fitness of the solution, our aim is to Maximize this fitness Respectively (Cutset, Power, Delay, Balance) Fitness Fuzzy cost function

22 Simulated Evolution Algorithm Simulated evolution Begin Start with an initial feasible Partition S Repeat Evaluation : Evaluate the G i (goodness) of all modules Selection : For each V i (cell) DO begin if Random Rm > G i then select the cell End For Allocation : For each selected V i (cell) DO begin Move the cell to destination Block. End For Until Stopping criteria is satisfied. Return best solution. End

23 Cut goodness d i : set of all nets, Connected and not cut. w i : set of all nets, Connected and cut.

24 Power Goodness V i is the set of all nets connected and Ui is the set of all nets connected and cut.

25 Delay Goodness Ki: is the set of cells in all paths passing by cell i. Li: is the set of cells in all paths passing by cell i and are not in same block as i.

26 Final selection Fuzzy rule IF Cell ‘i’ is near its optimal Cut-set goodness as compared to other cells AND AND THEN it has a high goodness. near its optimal net delay goodness as compared to other cells OR T (max) (i) is much smaller than T max near its optimal power goodness compared to other cells

27 T max :delay of most critical path in current iteration. T (max) (i) :delay of longest path traversing cell i. X path = T max / T (max) (i) Fuzzy Goodness Respectively (Cutset, Power, Delay ) goodness.

28 Experimental Results ISCAS Benchmark Circuits

29 SimE versus Tabu Search & GA against time Circuit: s13207

30 Experimental Results: SimE versus TS and GA SimE results were better than TS and GA, with faster execution time.

31 Conclusion :Re-write this The present work successfully addressed the important issue of reducing power and delay consumption in VLSI circuits. The present work successfully formulate and provide solutions to the problem of multi-objective VLSI partitioning. TS partitioning algorithm outperformed GA in terms of quality of solution and execution time.

32 Thank you